david/Repository
1
0
Fork 0
Code Releases Activity

Auto-commit: 2025-10-31 08:58:35

Browse Source
This commit is contained in:
David Wuibaille
2025-10-31 08:58:36 +01:00
parent 7d94414992
commit 7cc3011354
1088 changed files with 193455 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

38
Tools/RwPortableX64V1.6.7/Win64/Portable/25308086.IRW Normal file
View File

@@ -0,0 +1,38 @@
[INFO]
Name = Intel i850E North bridge
42 = DQS Output, Timing Control Register
48 = Clock Crossing Register
4E = DRAM Clocks Control Register
51 = AGP Miscellaneous Configuration Register
52 = Graphics Control Register
60 = DRAM Row 0 Boundary Register
61 = DRAM Row 1 Boundary Register
62 = DRAM Row 2 Boundary Register
63 = DRAM Row 3 Boundary Register
70 = DRAM Row 0/1 Attribute Register
71 = DRAM Row 2/3 Attribute Register
78 = DRAM Timing Register
7C = DRAM Controller Mode Register
88 = DRAM secondary control Register
90 = Programmable Attributes Map 0
91 = Programmable Attributes Map 1
92 = Programmable Attributes Map 2
93 = Programmable Attributes Map 3
94 = Programmable Attributes Map 4
95 = Programmable Attributes Map 5
96 = Programmable Attributes Map 6
97 = Fixed DRAM Hole Control Register
9D = System Management RAM Control Register
9E = Extended System Management RAM Control
A8 = AGP Command
B0 = AGP Control Register
B4 = Aperture Size
B8 = Aperture Translation Table
BC = AGP Interface Multi-Transaction Timer Register
BD = AGP Low Priority Transaction Timer Register
C6 = GMCH Configuration
C8 = Error Status
CA = Error Command
CC = SMI Command Register
CE = SCI Command Register
DE = Scratchpad Data Register

259
Tools/RwPortableX64V1.6.7/Win64/Portable/ATA.IRW Normal file
View File

@@ -0,0 +1,259 @@
[INFO]
00="General configuration"," B15 0=ATA device"," B7 1=Removable media"," B2 1=Response incomplete"
01="Obsolete"
02="Specific configuration"
03="Obsolete"
04="Retired"
05="Retired"
06="Obsolete"
07="Reserved for assignment by the CompactFlash Association"
08="Reserved for assignment by the CompactFlash Association"
09="Retired"
0A="Serial number (20 ASCII characters)"
0B="Serial number (20 ASCII characters)"
0C="Serial number (20 ASCII characters)"
0D="Serial number (20 ASCII characters)"
0E="Serial number (20 ASCII characters)"
0F="Serial number (20 ASCII characters)"
10="Serial number (20 ASCII characters)"
11="Serial number (20 ASCII characters)"
12="Serial number (20 ASCII characters)"
13="Serial number (20 ASCII characters)"
14="Retired"
15="Retired"
16="Obsolete"
17="Firmware revision (8 ASCII characters)"
18="Firmware revision (8 ASCII characters)"
19="Firmware revision (8 ASCII characters)"
1A="Firmware revision (8 ASCII characters)"
1B="Model number (40 ASCII characters)"
1C="Model number (40 ASCII characters)"
1D="Model number (40 ASCII characters)"
1E="Model number (40 ASCII characters)"
1F="Model number (40 ASCII characters)"
20="Model number (40 ASCII characters)"
21="Model number (40 ASCII characters)"
22="Model number (40 ASCII characters)"
23="Model number (40 ASCII characters)"
24="Model number (40 ASCII characters)"
25="Model number (40 ASCII characters)"
26="Model number (40 ASCII characters)"
27="Model number (40 ASCII characters)"
28="Model number (40 ASCII characters)"
29="Model number (40 ASCII characters)"
2A="Model number (40 ASCII characters)"
2B="Model number (40 ASCII characters)"
2C="Model number (40 ASCII characters)"
2D="Model number (40 ASCII characters)"
2E="Model number (40 ASCII characters)"
2F="B15:8 = 80h","B7:0 00h=Reserved"," 01h-FFh=Maximum number of sectors that shall be transferred per interrupt on READ/WRITE MULTIPLE commands"
30="Reserved"
31="Capabilities"," B15:14 Reserved"," B13 1=Standby timer values as specified in this standard are supported, 0=Standby timer values shall be managed by the device"," B12 Reserved"," B11 1=IORDY supported, 0=IORDY may be supported"," B10 1=IORDY may be disabled"," B9 1=LBA supported"," B8 1=DMA supported"
32="Capabilities"," B15=0"," B14=1"," B13:2=Reserved"," B1=Obsolete"," B0 Shall be set to one to indicate a device specific Standby timer value minimum"
33="Obsolete"
34="Obsolete"
35="B15:3=Reserved","B2 1=the fields reported in word 88 are valid, 0=the fields reported in word 88 are not valid","B1 1=the fields reported in words (70:64) are valid, 0=the fields reported in words (70:64) are not valid","B0=Obsolete"
36="Obsolete"
37="Obsolete"
38="Obsolete"
39="Obsolete"
3A="Obsolete"
3B="B15:9=Reserved","B8 1=Multiple sector setting is valid","B7:0 xxh=Current setting for number of sectors that shall be transferred per interrupt on R/W Multiple command"
3C="Total number of user addressable sectors"
3D="Total number of user addressable sectors"
3E="Obsolete"
3F="B15:11=Reserved","B10 1=Multiword DMA mode 2 is selected, 0=Multiword DMA mode 2 is not selected","B9 1=Multiword DMA mode 1 is selected, 0=Multiword DMA mode 1 is not selected","B8 1=Multiword DMA mode 0 is selected, 0=Multiword DMA mode 0 is not selected","B7:3=Reserved","B2 1=Multiword DMA mode 2 and below are supported","B1 1=Multiword DMA mode 1 and below are supported","B0 1=Multiword DMA mode 0 is supported"
40="B15:8=Reserved","B7:0 PIO modes supported"
41="Minimum Multiword DMA transfer cycle time per word"," B15:0 Cycle time in nanoseconds"
42="Manufacturer's recommended Multiword DMA transfer cycle time"," B15:0 Cycle time in nanoseconds"
43="Minimum PIO transfer cycle time without flow control"," B15:0 Cycle time in nanoseconds"
44="Minimum PIO transfer cycle time with IORDY flow control"," B15:0 Cycle time in nanoseconds"
45="Reserved (for future command overlap and queuing)"
46="Reserved (for future command overlap and queuing)"
47="Reserved for the IDENTIFY PACKET DEVICE command"
48="Reserved for the IDENTIFY PACKET DEVICE command"
49="Reserved for the IDENTIFY PACKET DEVICE command"
4A="Reserved for the IDENTIFY PACKET DEVICE command"
4B="Queue depth"," B15:5 Reserved"," B4:0 Maximum queue depth-1"
4C="Reserved for Serial ATA"
4D="Reserved for Serial ATA"
4E="Reserved for Serial ATA"
4F="Reserved for Serial ATA"
50="Major version number","0000h or FFFFh = device does not report version"," B14 ATA/ATAPI-14"," B13 ATA/ATAPI-13"," B12 ATA/ATAPI-12"," B11 ATA/ATAPI-11"," B10 ATA/ATAPI-10"," B9 ATA/ATAPI-9"," B8 ATA/ATAPI-8"," B7 ATA/ATAPI-7"," B6 ATA/ATAPI-6"," B5 ATA/ATAPI-5"," B4 ATA/ATAPI-4"
51="Minor version number","0000h or FFFFh = device does not report version","000Dh ATA/ATAPI-4 X3T13 1153D revision 6","000Eh ATA/ATAPI-4 T13 1153D revision 13","000Fh ATA/ATAPI-4 X3T13 1153D revision 7","0010h ATA/ATAPI-4 T13 1153D revision 18","0011h ATA/ATAPI-4 T13 1153D revision 15","0012h ATA/ATAPI-4 published, ANSI INCITS 317-1998","0013h ATA/ATAPI-5 T13 1321D revision 3","0014h ATA/ATAPI-4 T13 1153D revision 14","0015h ATA/ATAPI-5 T13 1321D revision 1","0016h ATA/ATAPI-5 published, ANSI INCITS 340-2000","0017h ATA/ATAPI-4 T13 1153D revision 17","0018h ATA/ATAPI-6 T13 1410D revision 0","0019h ATA/ATAPI-6 T13 1410D revision 3a","001Ah ATA/ATAPI-7 T13 1532D revision 1","001Bh ATA/ATAPI-6 T13 1410D revision 2","001Ch ATA/ATAPI-6 T13 1410D revision 1","001Eh ATA/ATAPI-7 T13 1532D revision 0","0021h ATA/ATAPI-7 T13 1532D revision 4a","0022h ATA/ATAPI-6 published, ANSI INCITS 361-2002"
52="Command set supported"," B14 1=NOP command supported"," B13 1=READ BUFFER command supported"," B12 1=WRITE BUFFER command supported"," B10 1=Host Protected Area feature set supported"," B9 1=DEVICE RESET command supported"," B8 1=SERVICE interrupt supported"," B7 1=release interrupt supported"," B6 1=look-ahead supported"," B5 1=write cache supported"," B4 Shall be cleared to zero to indicate that the PACKET Command feature set is not supported"," B3 1=mandatory Power Management feature set supported"," B2 1=Removable Media feature set supported"," B1 1=Security Mode feature set supported"," B0 1=SMART feature set supported"
53="Command sets supported"," B15 Shall be cleared to zero"," B14 Shall be set to one"," B13 FLUSH CACHE EXT command"," B12 mandatory FLUSH CACHE command"," B11 Device Configuration Overlay feature set"," B10 48-bit Address feature set"," B9 Automatic Acoustic Management feature set"," B8 SET MAX security extension"," B7 See Address Offset Reserved Area Boot, INCITS TR27:2001"," B6 SET FEATURES subcommand required to spinup after power-up"," B5 Power-Up In Standby feature set"," B4 Removable Media Status Notification feature set"," B3 Advanced Power Management feature set"," B2 CFA feature set"," B1 READ/WRITE DMA QUEUED"," B0 DOWNLOAD MICROCODE command","
54="Command set/feature supported extension"," B15 Shall be cleared to zero"," B14 Shall be set to one"," B13 IDLE IMMEDIATE with UNLOAD FEATURE"," B12 Reserved for technical report"," B11 Reserved for technical report"," B10 URG bit supported for WRITE STREAM DMA EXT and WRITE STREAM EXT"," B9 URG bit supported for READ STREAM DMA EXT and READ STREAM EXT"," B8 64-bit World wide name"," B7 WRITE DMA QUEUED FUA EXT command"," B6 WRITE DMA FUA EXT and WRITE MULTIPLE FUA EXT commands"," B5 General Purpose Logging feature set"," B4 Streaming feature set"," B3 Media Card Pass Through Command feature set"," B2 Media serial number"," B1 SMART self-test"," B0 SMART error logging"
55="Command set/feature enabled"," B15 Obsolete"," B14 NOP command enabled"," B13 READ BUFFER command enabled"," B12 WRITE BUFFER command enabled"," B11 Obsolete"," B10 Host Protected Area feature set enabled"," B9 DEVICE RESET command enabled"," B8 SERVICE interrupt enabled"," B7 release interrupt enabled"," B6 look-ahead enabled"," B5 write cache enabled"," B4 Shall be cleared to zero to indicate that the PACKET Command feature set is not supported"," B3 Power Management feature set enabled"," B2 Removable Media feature set enabled"," B1 Security Mode feature set enabled"," B0 SMART feature set enabled"
56="Command set/feature enabled","B15:14 Reserved","B13 FLUSH CACHE EXT command supported","B12 FLUSH CACHE command supported","B11 Device Configuration Overlay supported","B10 48-bit Address features set supported","B9 Automatic Acoustic Management feature set enabled","B8 SET MAX security extension enabled by SET MAX SET PASSWORD","B7 See Address Offset Reserved Area Boot, INCITS TR27:2001","B6 SET FEATURES subcommand required to spin-up after power-up","B5 Power-Up In Standby feature set enabled","B4 Removable Media Status Notification feature set enabled","B3 Advanced Power Management feature set enabled","B2 CFA feature set enabled","B1 READ/WRITE DMA QUEUED command supported","B0 DOWNLOAD MICROCODE command supported"
57="Command set/feature default","B15 Shall be cleared to zero","B14 Shall be set to one","B13 IDLE IMMEDIATE with UNLOAD FEATURE supported","B12 Reserved for technical report-","B11 Reserved for technical report-","B10 URG bit supported for WRITE STREAM DMA EXT and WRITE STREAM EXT","B9 URG bit supported for READ STREAM DMA EXT and READ STREAM EXT","B8 64 bit World wide name supported","B7 WRITE DMA QUEUED FUA EXT command supported","B6 WRITE DMA FUA EXT and WRITE MULTIPLE FUA EXT commands supported","B5 General Purpose Logging feature set supported","B4 Valid CONFIGURE STREAM command has been executed","B3 Media Card Pass Through Command feature set enabled","B2 Media serial number is valid","B1 SMART self-test supported","B0 SMART error logging supported"
58="B15 Reserved","B14 Ultra DMA mode 6 is selected","B13 Ultra DMA mode 5 is selected","B12 Ultra DMA mode 4 is selected","B11 Ultra DMA mode 3 is selected","B10 Ultra DMA mode 2 is selected","B9 Ultra DMA mode 1 is selected","B8 Ultra DMA mode 0 is selected","B7 Reserved","B6 Ultra DMA mode 6 and below are supported","B5 Ultra DMA mode 5 and below are supported","B4 Ultra DMA mode 4 and below are supported","B3 Ultra DMA mode 3 and below are supported","B2 Ultra DMA mode 2 and below are supported","B1 Ultra DMA mode 1 and below are supported","B0 Ultra DMA mode 0 is supported"
59="Time required for security erase unit completion"
5A="Time required for Enhanced security erase completion"
5B="Current advanced power management value"
5C="Master Password Revision Code"
5D="Hardware reset result. The contents of bits (12:0) of this word shall change only during the execution of a hardware reset","B15 Shall be cleared to zero.","B14 Shall be set to one.","B13 1=device detected CBLID- above ViH, 0=device detected CBLID- below ViL","B12:8 Device 1 hardware reset result. Device 0 shall clear these bits to zero. Device 1 shall set these bits as follows:"," B12 Reserved."," B11 0=Device 1 did not assert PDIAG-. 1=Device 1 asserted PDIAG-."," B10:9 These bits indicate how Device 1 determined the device number:"," 00=Reserved."," 01=a jumper was used."," 10=the CSEL signal was used."," 11=some other method was used or the method is unknown.","B8 Shall be set to one.","B7:0 Device 0 hardware reset result. Device 1 shall clear these bits to zero. Device 0 shall set these bits as follows:"," B7 Reserved"," B6 0=Device 0 does not respond when Device 1 is selected. 1=Device 0 responds when Device 1 is selected."," B5 0=Device 0 did not detect the assertion of DASP-. 1=Device 0 detected the assertion of DASP-."," B4 0=Device 0 did not detect the assertion of PDIAG-. 1=Device 0 detected the assertion of PDIAG-."," B3 0=Device 0 failed diagnostics. 1=Device 0 passed diagnostics."," B2:1 These bits indicate how Device 0 determined the device number:"," 00=Reserved."," 01=a jumper was used."," 10=the CSEL signal was used."," 11=some other method was used or the method is unknown.","B0 Shall be set to one."
5E="B15:8 Vendor's recommended acoustic management value","B7:0 Current automatic acoustic management value"
5F="Stream Minimum Request Size"
60="Streaming Transfer Time - DMA"
61="Streaming Access Latency - DMA and PIO"
62="Streaming Performance Granularity"
63="Streaming Performance Granularity"
64="Maximum user LBA for 48-bit Address feature set"
65="Maximum user LBA for 48-bit Address feature set"
66="Maximum user LBA for 48-bit Address feature set"
67="Maximum user LBA for 48-bit Address feature set"
68="Streaming Transfer Time - PIO"
69="Reserved"
6A="Physical sector size/Logical Sector Size","B15 Shall be cleared to zero","B14 Shall be set to one","B13 Device has multiple logical sectors per physical sector.","B12 Device Logical Sector Longer than 256 Words","B11:4 Reserved","B3:0 2X logical sectors per physical sector"
6B="Inter-seek delay for ISO-7779 acoustic testing in microseconds"
6C="B15:12 NAA (3:0)","B11:0 IEEE OUI (23:12)"
6D="B15:4 IEEE OUI (11:0)","B3:0 Unique ID (35:32)"
6E="B15:0 Unique ID (31:16)"
6F="B15:0 Unique ID (15:0)"
70="Reserved for world wide name extension to 128 bits"
71="Reserved for world wide name extension to 128 bits"
72="Reserved for world wide name extension to 128 bits"
73="Reserved for world wide name extension to 128 bits"
74="Reserved for technical report"
75="Words per Logical Sector"
76="Words per Logical Sector"
77="Reserved"
78="Reserved"
79="Reserved"
7A="Reserved"
7B="Reserved"
7C="Reserved"
7D="Reserved"
7E="Reserved"
7F="Removable Media Status Notification feature set support"," B15:2 Reserved"," B1:0 00=Removable Media Status Notification feature set not supported"," 01=Removable Media Status Notification feature supported"," 10=Reserved"," 11=Reserved"
80="Security status","B15:9 Reserved","B8 Security level 0=High, 1=Maximum","B7:6 Reserved","B5 Enhanced security erase supported","B4 Security count expired","B3 Security frozen","B2 Security locked","B1 Security enabled","B0 Security supported"
81="Vendor specific"
82="Vendor specific"
83="Vendor specific"
84="Vendor specific"
85="Vendor specific"
86="Vendor specific"
87="Vendor specific"
88="Vendor specific"
89="Vendor specific"
8A="Vendor specific"
8B="Vendor specific"
8C="Vendor specific"
8D="Vendor specific"
8E="Vendor specific"
8F="Vendor specific"
90="Vendor specific"
91="Vendor specific"
92="Vendor specific"
93="Vendor specific"
94="Vendor specific"
95="Vendor specific"
96="Vendor specific"
97="Vendor specific"
98="Vendor specific"
99="Vendor specific"
9A="Vendor specific"
9B="Vendor specific"
9C="Vendor specific"
9D="Vendor specific"
9E="Vendor specific"
9F="Vendor specific"
A0="CFA power mode 1","B15 Word 160 supported","B14 Reserved","B13 CFA power mode 1 is required for one or more commands implemented by the device","B12 CFA power mode 1 disabled","B11:0 Maximum current in ma"
A1="Reserved for assignment by the CompactFlash Association"
A2="Reserved for assignment by the CompactFlash Association"
A3="Reserved for assignment by the CompactFlash Association"
A4="Reserved for assignment by the CompactFlash Association"
A5="Reserved for assignment by the CompactFlash Association"
A6="Reserved for assignment by the CompactFlash Association"
A7="Reserved for assignment by the CompactFlash Association"
A8="Reserved for assignment by the CompactFlash Association"
A9="Reserved for assignment by the CompactFlash Association"
AA="Reserved for assignment by the CompactFlash Association"
AB="Reserved for assignment by the CompactFlash Association"
AC="Reserved for assignment by the CompactFlash Association"
AD="Reserved for assignment by the CompactFlash Association"
AE="Reserved for assignment by the CompactFlash Association"
AF="Reserved for assignment by the CompactFlash Association"
B0="Current media serial number"
B1="Current media serial number"
B2="Current media serial number"
B3="Current media serial number"
B4="Current media serial number"
B5="Current media serial number"
B6="Current media serial number"
B7="Current media serial number"
B8="Current media serial number"
B9="Current media serial number"
BA="Current media serial number"
BB="Current media serial number"
BC="Current media serial number"
BD="Current media serial number"
BE="Current media serial number"
BF="Current media serial number"
C0="Current media serial number"
C1="Current media serial number"
C2="Current media serial number"
C3="Current media serial number"
C4="Current media serial number"
C5="Current media serial number"
C6="Current media serial number"
C7="Current media serial number"
C8="Current media serial number"
C9="Current media serial number"
CA="Current media serial number"
CB="Current media serial number"
CC="Current media serial number"
CD="Current media serial number"
CE="Reserved"
CF="Reserved"
D0="Reserved"
D1="Reserved"
D2="Reserved"
D3="Reserved"
D4="Reserved"
D5="Reserved"
D6="Reserved"
D7="Reserved"
D8="Reserved"
D9="Reserved"
DA="Reserved"
DB="Reserved"
DC="Reserved"
DD="Reserved"
DE="Reserved"
DF="Reserved"
E0="Reserved"
E1="Reserved"
E2="Reserved"
E3="Reserved"
E4="Reserved"
E5="Reserved"
E6="Reserved"
E7="Reserved"
E8="Reserved"
E9="Reserved"
EA="Reserved"
EB="Reserved"
EC="Reserved"
ED="Reserved"
EE="Reserved"
EF="Reserved"
F0="Reserved"
F1="Reserved"
F2="Reserved"
F3="Reserved"
F4="Reserved"
F5="Reserved"
F6="Reserved"
F7="Reserved"
F8="Reserved"
F9="Reserved"
FA="Reserved"
FB="Reserved"
FC="Reserved"
FD="Reserved"
FE="Reserved"
FF="Integrity word","B15:8 Checksum","B7:0 Signature"

258
Tools/RwPortableX64V1.6.7/Win64/Portable/ATAPI.IRW Normal file
View File

@@ -0,0 +1,258 @@
[INFO]
00="General configuration","B15:14 10=ATAPI device, 11=Reserved","B13 Reserved","B12:8 Field indicates command packet set used by device","B7 1=removable media device","B6:5 00=Device shall set DRQ to one within 3 ms of receiving PACKET command."," 01=Obsolete"," 10=Device shall set DRQ to one within 50 <20>gs of receiving PACKET command."," 11=Reserved","B4:3 Reserved","B2 Incomplete response","B1:0 00=12 byte command packet"," 01=16 byte command packet"," 1x=Reserved"
01="Obsolete"
02="Unique configuration"
03="Reserved"
04="Reserved"
05="Reserved"
06="Reserved"
07="Reserved"
08="Reserved"
09="Reserved"
0A="Serial number (20 ASCII characters)"
0B="Serial number (20 ASCII characters)"
0C="Serial number (20 ASCII characters)"
0D="Serial number (20 ASCII characters)"
0E="Serial number (20 ASCII characters)"
0F="Serial number (20 ASCII characters)"
10="Serial number (20 ASCII characters)"
11="Serial number (20 ASCII characters)"
12="Serial number (20 ASCII characters)"
13="Serial number (20 ASCII characters)"
14="Reserved"
15="Reserved"
16="Reserved"
17="Firmware revision (8 ASCII characters)"
18="Firmware revision (8 ASCII characters)"
19="Firmware revision (8 ASCII characters)"
1A="Firmware revision (8 ASCII characters)"
1B="Model number (40 ASCII characters)"
1C="Model number (40 ASCII characters)"
1D="Model number (40 ASCII characters)"
1E="Model number (40 ASCII characters)"
1F="Model number (40 ASCII characters)"
20="Model number (40 ASCII characters)"
21="Model number (40 ASCII characters)"
22="Model number (40 ASCII characters)"
23="Model number (40 ASCII characters)"
24="Model number (40 ASCII characters)"
25="Model number (40 ASCII characters)"
26="Model number (40 ASCII characters)"
27="Model number (40 ASCII characters)"
28="Model number (40 ASCII characters)"
29="Model number (40 ASCII characters)"
2A="Model number (40 ASCII characters)"
2B="Model number (40 ASCII characters)"
2C="Model number (40 ASCII characters)"
2D="Model number (40 ASCII characters)"
2E="Model number (40 ASCII characters)"
2F="Reserved"
30="Reserved"
31="Capabilities","B15 interleaved DMA supported. Devices which require the DMADIR bit in the Packet command shall clear this bit to 0.","B14 command queuing supported","B13 overlap operation supported","B12 ATA software reset required (Obsolete)","B11 IORDY supported","B10 IORDY may be disabled","B9 Shall be set to one.","B8 DMA supported. Devices which require the DMADIR bit in the Packet command shall clear this bit to 0","B7:0 Vendor specific"
32="Capabilities","B15 Shall be cleared to zero","B14 Shall be set to one","B13:2 Reserved","B1 Obsolete","B0 Shall be set to one to indicate a device specific Standby timer value minimum"
33="Obsolete"
34="Obsolete"
35="B15:3=Reserved","B2 1=the fields reported in word 88 are valid, 0=the fields reported in word 88 are not valid","B1 1=the fields reported in words (70:64) are valid, 0=the fields reported in words (70:64) are not valid","B0=Obsolete"
36="Reserved"
37="Reserved"
38="Reserved"
39="Reserved"
3A="Reserved"
3B="Reserved"
3C="Reserved"
3D="Reserved"
3E="B15 1=DMADIR bit in the Packet command is required for DMA transfers, 0=DMADIR bit in Packet command is not required for DMA transfers","B14:11 Reserved","B10 1=DMA is supported","B9 1=Multiword DMA mode 2 is supported","B8 1=Multiword DMA mode 1 is supported","B7 1=Multiword DMA mode 0 is supported","B6 1=Ultra DMA mode 6 and below are supported","B5 1=Ultra DMA mode 5 and below are supported","B4 1=Ultra DMA mode 4 and below are supported","B3 1=Ultra DMA mode 3 and below are supported","B2 1=Ultra DMA mode 2 and below are supported","B1 1=Ultra DMA mode 1 and below are supported","B0 1=Ultra DMA mode 0 is supported"
3F="B15-11 Reserved","B10 1=Multiword DMA mode 2 is selected"," 0=Multiword DMA mode 2 is not selected","B9 1=Multiword DMA mode 1 is selected"," 0=Multiword DMA mode 1 is not selected","B8 1=Multiword DMA mode 0 is selected"," 0=Multiword DMA mode 0 is not selected","B7-3 Reserved","B2 1=Multiword DMA mode 2 and below are supported. Devices which require the DMADIR bit in the Packet command shall clear this bit to 0.","B1 1=Multiword DMA mode 1 and below are supported. Devices which require the DMADIR bit in the Packet command shall clear this bit to 0.","B0 1=Multiword DMA mode 0 is supported Multiword DMA mode selected. Devices which require the DMADIR bit in the Packet command shall clear this bit to 0."
40="B15:8=Reserved","B7:0 PIO modes supported"
41="Minimum Multiword DMA transfer cycle time per word"," B15:0 Cycle time in nanoseconds"
42="Manufacturer's recommended Multiword DMA transfer cycle time"," B15:0 Cycle time in nanoseconds"
43="Minimum PIO transfer cycle time without flow control"," B15:0 Cycle time in nanoseconds"
44="Minimum PIO transfer cycle time with IORDY flow control"," B15:0 Cycle time in nanoseconds"
45="Reserved (for future command overlap and queuing)"
46="Reserved (for future command overlap and queuing)"
47="Typical time in ns from receipt of PACKET command to bus release"
48="Typical time in ns from receipt of SERVICE command to BSY cleared to zero"
49="Reserved"
4A="Reserved"
4B="Queue depth"," B15:5 Reserved"," B4:0 Maximum queue depth-1"
4C="Reserved for Serial ATA"
4D="Reserved for Serial ATA"
4E="Reserved for Serial ATA"
4F="Reserved for Serial ATA"
50="Major version number","0000h or FFFFh = device does not report version"," B14 ATA/ATAPI-14"," B13 ATA/ATAPI-13"," B12 ATA/ATAPI-12"," B11 ATA/ATAPI-11"," B10 ATA/ATAPI-10"," B9 ATA/ATAPI-9"," B8 ATA/ATAPI-8"," B7 ATA/ATAPI-7"," B6 ATA/ATAPI-6"," B5 ATA/ATAPI-5"," B4 ATA/ATAPI-4"
51="Minor version number","0000h or FFFFh = device does not report version","000Dh ATA/ATAPI-4 X3T13 1153D revision 6","000Eh ATA/ATAPI-4 T13 1153D revision 13","000Fh ATA/ATAPI-4 X3T13 1153D revision 7","0010h ATA/ATAPI-4 T13 1153D revision 18","0011h ATA/ATAPI-4 T13 1153D revision 15","0012h ATA/ATAPI-4 published, ANSI INCITS 317-1998","0013h ATA/ATAPI-5 T13 1321D revision 3","0014h ATA/ATAPI-4 T13 1153D revision 14","0015h ATA/ATAPI-5 T13 1321D revision 1","0016h ATA/ATAPI-5 published, ANSI INCITS 340-2000","0017h ATA/ATAPI-4 T13 1153D revision 17","0018h ATA/ATAPI-6 T13 1410D revision 0","0019h ATA/ATAPI-6 T13 1410D revision 3a","001Ah ATA/ATAPI-7 T13 1532D revision 1","001Bh ATA/ATAPI-6 T13 1410D revision 2","001Ch ATA/ATAPI-6 T13 1410D revision 1","001Eh ATA/ATAPI-7 T13 1532D revision 0","0021h ATA/ATAPI-7 T13 1532D revision 4a","0022h ATA/ATAPI-6 published, ANSI INCITS 361-2002"
52="Command set supported. If words (83:82) = 0000h or FFFFh command set notification not supported","B15 Obsolete","B14 NOP command supported","B13 READ BUFFER command supported","B12 WRITE BUFFER command supported","B11 Obsolete","B10 Host Protected Area feature set supported","B9 DEVICE RESET command supported","B8 SERVICE interrupt supported","B7 release interrupt supported","B6 look-ahead supported","B5 write cache supported","B4 Shall be set to one indicating the PACKET Command feature set is supported.","B3 Power Management feature set supported","B2 Removable Media feature set supported","B1 Security Mode feature set supported","B0 SMART feature set supported"
53="Command sets supported. If words (83:82) = 0000h or FFFFh command set notification not supported","B15 Shall be cleared to zero","B14 Shall be set to one","B13 Reserved","B12 1=FLUSH CACHE command supported","B11 1=Device Configuration Overlay feature set supported","B10 Reserved","B9 1=AUTOMATIC Acoustic Management feature set supported","B8 1=SET MAX security extension supported","B7 See Address Offset Reserved Area Boot, INCITS TR27:2001","B6 1=SET FEATURES subcommand required to spinup after power-up","B5 1=Power-Up In Standby feature set supported","B4 1=Removable Media Status Notification feature set supported","B3:1 Reserved","B0 1=DOWNLOAD MICROCODE command supported"
54="Command set/feature supported extension. If words 82, 83, and 84 = 0000h or FFFFh command set notification extension is not supported.","B15 Shall be cleared to zero","B14 Shall be set to one","B13:0 Reserved"
55="Command set/feature enabled. If words 85, 86, and 87 = 0000h or FFFFh command set enabled","notification is not supported.","B15 Obsolete","B14 1 = NOP command enabled","B13 1 = READ BUFFER command enabled","B12 1 = WRITE BUFFER command enabled","B11 Obsolete","B10 1 = Host Protected Area feature set enabled","B9 1 = DEVICE RESET command enabled","B8 1 = SERVICE interrupt enabled","B7 1 = release interrupt enabled","B6 1 = look-ahead enabled","B5 1 = write cache enabled","B4 Shall be set to one indicating the PACKET Command feature set is supported.","B3 1 = Power Management feature set enabled","B2 1 = Removable Media feature set enabled","B1 1 = Security Mode feature set enabled","B0 1 = SMART feature set enabled"
56="Command set/feature enabled. If words 85, 86, and 87 = 0000h or FFFFh command set enabled notification is not supported.","B15-13 Reserved","B12 1 = FLUSH CACHE command supported","B11 1 = Device Configuration Overlay feature set supported","B10 Reserved","B9 1 = Automatic Acoustic Management feature set enabled","B8 1 = SET MAX security extension enabled by a SET MAX SET PASSWORD","B7 See Address Offset Reserved Area Boot, INCITS TR27:2001","B6 1 = SET FEATURES subcommand required to spinup after power-up","B5 1 = Power-Up In Standby feature set enabled","B4 1 = Removable Media Status Notification feature set enabled via the SET FEATURES command.","B3-1 Reserved","B0 1 = DOWNLOAD MICROCODE command enabled"
57="Command set/feature default. If words 85, 86, and 87 = 0000h or FFFFh command set default notification is not supported.","B15 Shall be cleared to zero","B14 Shall be set to one","B13-0 Reserved"
58="B15 Reserved","B14 1=Ultra DMA mode 6 is selected","B13 1=Ultra DMA mode 5 is selected","B12 1=Ultra DMA mode 4 is selected","B11 1=Ultra DMA mode 3 is selected","B10 1=Ultra DMA mode 2 is selected","B9 1=Ultra DMA mode 1 is selected","B8 1=Ultra DMA mode 0 is selected","B7 Reserved","B6 1=Ultra DMA mode 6 and below are supported, 0=Devices require the DMADIR bit in the Packet command.","B5 1=Ultra DMA mode 5 and below are supported, 0=Devices require the DMADIR bit in the Packet command.","B4 1=Ultra DMA mode 4 and below are supported, 0=Devices require the DMADIR bit in the Packet command.","B3 1=Ultra DMA mode 3 and below are supported, 0=Devices require the DMADIR bit in the Packet command.","B2 1=Ultra DMA mode 2 and below are supported, 0=Devices require the DMADIR bit in the Packet command.","B1 1=Ultra DMA mode 1 and below are supported, 0=Devices require the DMADIR bit in the Packet command.","B0 1=Ultra DMA mode 0 is supported, 0=Devices require the DMADIR bit in the Packet command."
59="Reserved"
5A="Reserved"
5B="Reserved"
5C="Reserved"
5D="Hardware reset result. The contents of bits (12:0) of this word shall change only during the execution of a hardware reset","B15 Shall be cleared to zero.","B14 Shall be set to one.","B13 1=device detected CBLID- above ViH, 0=device detected CBLID- below ViL","B12:8 Device 1 hardware reset result. Device 0 shall clear these bits to zero. Device 1 shall set these bits as follows:"," B12 Reserved."," B11 0=Device 1 did not assert PDIAG-. 1=Device 1 asserted PDIAG-."," B10:9 These bits indicate how Device 1 determined the device number:"," 00=Reserved."," 01=a jumper was used."," 10=the CSEL signal was used."," 11=some other method was used or the method is unknown.","B8 Shall be set to one.","B7:0 Device 0 hardware reset result. Device 1 shall clear these bits to zero. Device 0 shall set these bits as follows:"," B7 Reserved"," B6 0=Device 0 does not respond when Device 1 is selected. 1=Device 0 responds when Device 1 is selected."," B5 0=Device 0 did not detect the assertion of DASP-. 1=Device 0 detected the assertion of DASP-."," B4 0=Device 0 did not detect the assertion of PDIAG-. 1=Device 0 detected the assertion of PDIAG-."," B3 0=Device 0 failed diagnostics. 1=Device 0 passed diagnostics."," B2:1 These bits indicate how Device 0 determined the device number:"," 00=Reserved."," 01=a jumper was used."," 10=the CSEL signal was used."," 11=some other method was used or the method is unknown.","B0 Shall be set to one."
5E="B15:8 Vendor's recommended acoustic management value","B7:0 Current automatic acoustic management value"
5F="Reserved"
60="Reserved"
61="Reserved"
62="Reserved"
63="Reserved"
64="Reserved"
65="Reserved"
66="Reserved"
67="Reserved"
68="Reserved"
69="Reserved"
6A="Reserved"
6B="Reserved"
6C="Reserved"
6D="Reserved"
6E="Reserved"
6F="Reserved"
70="Reserved"
71="Reserved"
72="Reserved"
73="Reserved"
74="Reserved"
75="Reserved"
76="Reserved"
77="Reserved"
78="Reserved"
79="Reserved"
7A="Reserved"
7B="Reserved"
7C="Reserved"
7D="ATAPI byte count = 0 behavior"
7E="Obsolete"
7F="Removable Media Status Notification feature set support"," B15:2 Reserved"," B1:0 00=Removable Media Status Notification feature set not supported"," 01=Removable Media Status Notification feature supported"," 10=Reserved"," 11=Reserved"
80="Security status","B15:9 Reserved","B8 Security level 0=High, 1=Maximum","B7:6 Reserved","B5 Enhanced security erase supported","B4 Security count expired","B3 Security frozen","B2 Security locked","B1 Security enabled","B0 Security supported"
81="Vendor specific"
82="Vendor specific"
83="Vendor specific"
84="Vendor specific"
85="Vendor specific"
86="Vendor specific"
87="Vendor specific"
88="Vendor specific"
89="Vendor specific"
8A="Vendor specific"
8C="Vendor specific"
8D="Vendor specific"
8E="Vendor specific"
8F="Vendor specific"
90="Vendor specific"
91="Vendor specific"
92="Vendor specific"
93="Vendor specific"
94="Vendor specific"
95="Vendor specific"
96="Vendor specific"
97="Vendor specific"
98="Vendor specific"
99="Vendor specific"
9A="Vendor specific"
9B="Vendor specific"
9C="Vendor specific"
9D="Vendor specific"
9E="Vendor specific"
9F="Vendor specific"
A0="Reserved for assignment by the CompactFlash Association"
A1="Reserved for assignment by the CompactFlash Association"
A2="Reserved for assignment by the CompactFlash Association"
A3="Reserved for assignment by the CompactFlash Association"
A4="Reserved for assignment by the CompactFlash Association"
A5="Reserved for assignment by the CompactFlash Association"
A6="Reserved for assignment by the CompactFlash Association"
A7="Reserved for assignment by the CompactFlash Association"
A8="Reserved for assignment by the CompactFlash Association"
A9="Reserved for assignment by the CompactFlash Association"
AA="Reserved for assignment by the CompactFlash Association"
AB="Reserved for assignment by the CompactFlash Association"
AC="Reserved for assignment by the CompactFlash Association"
AD="Reserved for assignment by the CompactFlash Association"
AE="Reserved for assignment by the CompactFlash Association"
AF="Reserved for assignment by the CompactFlash Association"
B0="Reserved"
B1="Reserved"
B2="Reserved"
B3="Reserved"
B4="Reserved"
B5="Reserved"
B6="Reserved"
B7="Reserved"
B8="Reserved"
B9="Reserved"
BA="Reserved"
BB="Reserved"
BC="Reserved"
BD="Reserved"
BE="Reserved"
BF="Reserved"
C0="Reserved"
C1="Reserved"
C2="Reserved"
C3="Reserved"
C4="Reserved"
C5="Reserved"
C6="Reserved"
C7="Reserved"
C8="Reserved"
C9="Reserved"
CA="Reserved"
CB="Reserved"
CC="Reserved"
CD="Reserved"
CE="Reserved"
CF="Reserved"
D0="Reserved"
D1="Reserved"
D2="Reserved"
D3="Reserved"
D4="Reserved"
D5="Reserved"
D6="Reserved"
D7="Reserved"
D8="Reserved"
D9="Reserved"
DA="Reserved"
DB="Reserved"
DC="Reserved"
DD="Reserved"
DE="Reserved"
DF="Reserved"
E0="Reserved"
E1="Reserved"
E2="Reserved"
E3="Reserved"
E4="Reserved"
E5="Reserved"
E6="Reserved"
E7="Reserved"
E8="Reserved"
E9="Reserved"
EA="Reserved"
EB="Reserved"
EC="Reserved"
ED="Reserved"
EE="Reserved"
EF="Reserved"
F0="Reserved"
F1="Reserved"
F2="Reserved"
F3="Reserved"
F4="Reserved"
F5="Reserved"
F6="Reserved"
F7="Reserved"
F8="Reserved"
F9="Reserved"
FA="Reserved"
FB="Reserved"
FC="Reserved"
FD="Reserved"
FE="Reserved"
FF="Integrity word","B15:8 Checksum","B7:0 Signature"

130
Tools/RwPortableX64V1.6.7/Win64/Portable/DDR2SPD.IRW Normal file
View File

@@ -0,0 +1,130 @@
[INFO]
Name = DDR2 SDRAM SPD
00 = Number of Serial PD bytes written during module manufacturer\r 01 = 1 byte\r 02 = 2 bytes\r 03 = 3 bytes\r . .\r . .\r 80 = 128 bytes\r . .
01 = Total number of bytes in Serial PD device\r 01 = 2 bytes\r 02 = 4 bytes\r 03 = 8 bytes\r . .\r . .\r 07 = 128 bytes\r 08 = 256 bytes\r . .
02 = Fundamental memory type\r 01 = FPM\r 02 = EDO\r 03 = Pipelined Nibble\r 04 = SDR SDRAM\r 05 = ROM\r 06 = DDR SGRAM\r 07 = DDR SDRAM\r 08 = DDR2 SDRAM
03 = Number of row addresses (includes Mixed-size Row addr) This field describes the Row addressing on the module. If there is one physical bank on the module or if there are two physical banks of the same size and organization, then bits 0-3 are used to represent the number of row addresses for each physical bank. If the module has two physical banks of asymmetric size, then bits 0-3 represent the number of row addresses for physical bank 1 and bits 4-7 represent the number of row addresses for physical bank 2 (bank 2 device is 2x bank 1 device width).
04 = Number of column addresses (includes Mixed-size Col addr) This field describes the Column addressing on the module. If there is one physical bank on the module or if there are two physical banks of the same size, then bits 0-3 are used to represent the number of column addresses for each physical bank. If the module has two physical banks of asymmetric size, then bits 0-3 represent the number of column addresses for physical bank 1 and bits 4-7 represent the number of column addresses for physical bank 2 (bank 2 device is 2x bank 1 device width).
05 = Number of physical banks on DIMM
06 = Module Data Width, Bytes 6 and 7 are used to designate the module<6C><65>s data width. The data width is presented as a 16-bit word: bit 0 of byte 6 becomes the LSB of the 16 bit width identifier and bit 7 of byte 7 becomes the MSB. Consequently, if the module has a width of less than 255 bits, byte 7 will be 00h. If the data width is 256 bits or more, byte 7 is used in conjunction with byte 6 to designate the total module width.
07 = Module Data Width, Bytes 6 and 7 are used to designate the module<6C><65>s data width. The data width is presented as a 16-bit word: bit 0 of byte 6 becomes the LSB of the 16 bit width identifier and bit 7 of byte 7 becomes the MSB. Consequently, if the module has a width of less than 255 bits, byte 7 will be 00h. If the data width is 256 bits or more, byte 7 is used in conjunction with byte 6 to designate the total module width.
08 = Voltage Interface Level of this assembly\r 0 = TTL/5V tolerant\r 1 = 1 LVTTL (not 5V tolerant)\r 2 = HSTL 1.5V\r 3 = SSTL 3.3V\r 4 = SSTL 2.5V
09 = SDRAM Cycle time, CL=X (highest CAS latency), This byte defines the minimum cycle time for the SDRAM device at the highest CAS Latency, CAS Latency=X, defined in byte 18. Byte 9, Cycle time for CAS Latency=X, is split into two nibbles: the higher order nibble (bits 4-7) designates the cycle time to a granularity of 1ns; the value presented by the lower order nibble (bits 0-3) has a granularity of .1ns and is added to the value designated by the higher nibble.
0A = SDRAM Access from Clock (highest CAS latency), This byte defines the maximum clock to data out time () for the SDRAM device. This is the Clock to data out specification at the highest given CAS Latency specified in byte 18 of this SPD specification. The byte is split into two nibbles: the higher order nibble (bits 4-7) designate the access time to a granularity of 0.1ns; the value presented by the lower order nibble (bits 0-3) has the granularity of .01ns and is added to the value designated by the higher nibble.
0B = DIMM configuration type, This byte describes the module's error detection and/or correction scheme.\r 0 = None\r 1 = Parity\r 2 = ECC
0C = Refresh Rate/Type\r 00 = Normal (15.625 us)\r 01 = Reduced (.25x) 3.9us\r 02 = Reduced (.5x) 7.8us\r 03 = Extended (2x) 31.3us\r 04 = Extended (4x) 62.5us\r 05 = Extended (8x) 125us\rSelf Refresh Entries\r 80 = Normal (15.625 us)\r 81 = Reduced (.25x) 3.9us\r 82 = Reduced (.5x) 7.8us\r 83 = Extended (2x) 31.3us\r 84 = Extended (4x) 62.5us\r 85 = Extended (8x) 125us
0D = Primary SDRAM Width, B6:0 = width of the primary data SDRAM. B7 = 1 - when there is a second physical bank on the module which is of different size from the first physical bank (the second physical bank's data RAMs are 2X the width of those on the first physical bank). If there is a second physical bank of the same size and configuration as the first, then bit 7 remains as 0 and primary SDRAM width for both banks is expressed using bits 0-6.
0E = Error Checking SDRAM width, If the module incorporates error checking and if the primary data SDRAM does not include these bits - i.e. there are separate error checking SDRAMs <20>X then the error checking SDRAM<41><4D>s width is expressed in this byte. B6:0 = Error checking SDRAM<41><4D>s width. B7 = 1 - when the module has a second physical bank that is a different size than the first physical bank. Bit 7 set to 1 indicates that Bank 2's error checking RAMs are 2X the width of those on the first physical bank.
0F = SDRAM Device Attributes <20>V Minimum Clock Delay, Back-to-Back Random Column Access
10 = Burst Lengths Supported. This byte describes which various programmable burst lengths are supported by the devices on the module. If the bit is 1, then that Burst Length is supported on the module; if the bit is 0, then that Burst Length is not supported by the module.
11 = SDRAM Device Attributes <20>V Number of Banks on SDRAM Device
12 = CAS# Latencies Supported. This byte describes which of the programmable CAS latencies (CAS to data out) are acceptable for the SDRAM devices used on the module.\r B2 = 2\r B3 = 3\r B4 = 4\r B5 = 5
13 = CS# Latency. Tthis byte defines the Chip Select (CS) latency associated with the SDRAM devices used on the module.\r B0 = 0\r B1 = 1\r B2 = 2\r B3 = 3\r B4 = 4\r B5 = 5\r B6 = 6
14 = Write Latency. This byte defines the write (W) latency associated with the SDRAM devices used on the module.\r B0 = 0\r B1 = 1\r B2 = 2\r B3 = 3
15 = SDRAM Module Attributes
16 = SDRAM Device Attributes
17 = Minimum SDRAM Cycle time at CL X-1 (2nd highest CAS latency)
18 = Maximum Data Access Time (tAC) from Clock at CLX-1 (2nd highest CAS latency)
19 = Minimum Clock Cycle at CLX-2 (3rd highest CAS latency)
1A = SDRAM Device Maximum Data Access Time (tAC) from Clock at CLX-2 (3rd highest CAS latency)
1B = Minimum Row Precharge Time (tRP), the higher order bits (bits 2-7) designate the time to a granularity of 1ns; the value presented by the lower order bits (bits 0-1) has a granularity of .25ns and is added to the value designated by the higher bits.
1C = Minimum Row Active to Row Active delay (tRRD), the higher order bits (bits 2-7) designate the time to a granularity of 1ns; the value presented by the lower order bits (bits 0-1) has a granularity of .25ns and is added to the value designated by the higher bits.
1D = Minimum RAS to CAS delay (tRCD), the higher order bits (bits 2-7) designate the time to a granularity of 1ns; the value presented by the lower order bits (bits 0-1) has a granularity of .25ns and is added to the value designated by the higher bits.
1E = Minimum Active to Precharge Time (tRAS), This byte identifies the minimum active to precharge time.
1F = Density of each row on module (mixed, non-mixed sizes), This byte describes the density of each physical bank on the SRAM DIMM. This byte will have at least one bit set to 1 to represent at least one bank's density. If there are more than one physical bank on the module (as represented in byte 5), and they have the same density, then only one bit is set in this field. If the module has more than one physical bank of different sizes, then more than one bit will be set; each bit set for each density represented.
20 = Address and Command Input Setup Time Before Clock, This field describes the input setup time before the rising edge of the clock at the SDRAM device on unbuffered modules, or at the register on registered modules. The byte is split into two nibbles: the higher order nibble (bits 4-7) designate the access time to a granularity of 0.1ns; the value presented by the lower order nibble (bits 0-3) has the granularity of .01ns and is added to the value designated by the higher nibble.
21 = Address and Command Input Hold Time After Clock, This field describes the input hold time after the rising edge of the clock at the SDRAM device on unbuffered modules, or at the register on registered modules. The byte is split into two nibbles: the higher order nibble (bits 4-7) designate the access time to a granularity of 0.1ns; the value presented by the lower order nibble (bits 0-3) has the granularity of .01ns and is added to the value designated by the higher nibble.
22 = Device Data/Data Mask Input Setup Time Before Data Strobe, This field describes the input setup time before the rising or falling edge of the Data Strobe. The byte is split into two nibbles: the higher order nibble (bits 4-7) designates the time to a granularity of 0.1ns; the value presented by the lower order nibble (bits 0-3) has the granularity of .01ns and is added to the value designated by the higher nibble.
23 = Device Data/Data Mask Input Hold Time After Data Strobe, This field describes the input hold time after the rising or falling edge of the Data Strobe. The byte is split into two nibbles: the higher order nibble (bits 4-7) designates the time to a granularity of 0.1ns; the value presented by the lower order nibble (bits 0-3) has the granularity of .01ns and is added to the value designated by the higher nibble.
24 = Reserved for VCSDRAM
25 = Reserved for VCSDRAM
26 = Reserved for VCSDRAM
27 = Reserved for VCSDRAM
28 = Reserved for VCSDRAM
29 = SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC), This byte identifies the minimum active to active or auto refresh time.
2A = SDRAM Device Minimum Auto<74>VRefresh to Active/Auto<74>VRefresh (tRFC), This byte identifies the minimum Auto-refresh to Active/Auto-Refresh command period.
2B = SDRAM Device Maximum device cycle time (tCKmax), This byte identifies the maximum device cycle time at any CAS latency, in nanoseconds. one special reserved value, FF, is used to describe devices which have no maximum cycle time. This byte split into two pieces: the higher order bits (bits 2-7) designate the time to a granularity of 1ns; the value presented by the lower order bits (bits 0-1) has a granularity of .25ns and is added to the value designated by the higher bits.
2C = SDRAM Device Maximum skew between DQS and DQ signals (tDQSQ), This byte identifies the maximum skew between DQS and associated DQ signals for each device, in hundredths of nanoseconds.
2D = DDR SDRAM Device Maximum Read DataHold Skew Factor (tQHS), This byte identifies the maximum skew factor used in the calculation of read data hold time from edges of DQS, specifically tQH = tHP - tQHS where tQHS is the read data hold skew factor. This SPD byte is split into two nibbles: the higher order nibble (bits 4-7) designate the access time to a granulartiy of 0.01 ns; the value presented by the lower order nibble (bits 0-3) has the granularity of 0.01ns and is added to the value designated by the higher nibble.
2E = Superset information (may be used in future)
2F = Superset information (may be used in future)
30 = Superset information (may be used in future)
31 = Superset information (may be used in future)
32 = Superset information (may be used in future)
33 = Superset information (may be used in future)
34 = Superset information (may be used in future)
35 = Superset information (may be used in future)
36 = Superset information (may be used in future)
37 = Superset information (may be used in future)
38 = Superset information (may be used in future)
39 = Superset information (may be used in future)
3A = Superset information (may be used in future)
3B = Superset information (may be used in future)
3C = Superset information (may be used in future)
3D = Superset information (may be used in future)
3E = SPD Revision
3F = Checksum for Bytes 0-62 (00h - 3Eh)
40 = Manufacturer's JEDEC ID code per JEP-108E
41 = Manufacturer's JEDEC ID code per JEP-108E
42 = Manufacturer's JEDEC ID code per JEP-108E
43 = Manufacturer's JEDEC ID code per JEP-108E
44 = Manufacturer's JEDEC ID code per JEP-108E
45 = Manufacturer's JEDEC ID code per JEP-108E
46 = Manufacturer's JEDEC ID code per JEP-108E
47 = Manufacturer's JEDEC ID code per JEP-108E
48 = Manufacturing Location
49 = Manufacturer's Part Number
4A = Manufacturer's Part Number
4B = Manufacturer's Part Number
4C = Manufacturer's Part Number
4D = Manufacturer's Part Number
4E = Manufacturer's Part Number
4F = Manufacturer's Part Number
50 = Manufacturer's Part Number
51 = Manufacturer's Part Number
52 = Manufacturer's Part Number
53 = Manufacturer's Part Number
54 = Manufacturer's Part Number
55 = Manufacturer's Part Number
56 = Manufacturer's Part Number
57 = Manufacturer's Part Number
58 = Manufacturer's Part Number
59 = Manufacturer's Part Number
5A = Manufacturer's Part Number
5B = Revision Code
5C = Revision Code
5D = Manufacturing Date
5E = Manufacturing Date
5F = Assembly Serial Number
60 = Assembly Serial Number
61 = Assembly Serial Number
62 = Assembly Serial Number
63 = Manufacturer Specific Data
64 = Manufacturer Specific Data
65 = Manufacturer Specific Data
66 = Manufacturer Specific Data
67 = Manufacturer Specific Data
68 = Manufacturer Specific Data
69 = Manufacturer Specific Data
6A = Manufacturer Specific Data
6B = Manufacturer Specific Data
6C = Manufacturer Specific Data
6D = Manufacturer Specific Data
6E = Manufacturer Specific Data
6F = Manufacturer Specific Data
70 = Manufacturer Specific Data
71 = Manufacturer Specific Data
72 = Manufacturer Specific Data
73 = Manufacturer Specific Data
74 = Manufacturer Specific Data
75 = Manufacturer Specific Data
76 = Manufacturer Specific Data
77 = Manufacturer Specific Data
78 = Manufacturer Specific Data
79 = Manufacturer Specific Data
7A = Manufacturer Specific Data
7B = Manufacturer Specific Data
7C = Manufacturer Specific Data
7D = Manufacturer Specific Data
7E = Intel specification frequency
7F = Intel Specification CAS# Latency support

259
Tools/RwPortableX64V1.6.7/Win64/Portable/DDR3SPD.IRW Normal file
View File

@@ -0,0 +1,259 @@
[INFO]
Name = DDR3 SDRAM SPD
00 = Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage\r b[3:0] SPD bytes used: 1=128, 2=176, 3=256\r b[6:4] SPD bytes total: 0=undefined, 1=256\r b7 CRC coverage: 0=0-125, 1=0-116
01 = SPD Revision\r b[7:4]: Encoding Level\r b[3:0]: Additions Level\r example: 0x10=revision 1.0
02 = Key Byte / DRAM Device Type\r 1=FPM\r 2=EDO\r 3=Pipelined Nibble\r 4=SDR SDRAM\r 5=ROM\r 6=DDR SGRAM\r 7=DDR SDRAM\r 8=DDR2 SDRAM\r 9=DDR2 SDRAM FB-DIMM\r 10=DDR2 SDRAM FB-DIMM PROBE\r 11=DDR3 SDRAM
03 = Key Byte / Module Type\r b[3:0]: 0=Undefined\r 1=RDIMM (width=133.35 mm nom)\r 2=UDIMM (width=133.35 mm nom)\r 3=SO-DIMM (width=67.6 mm nom)\r 4=Micro-DIMM (width=TBD mm nom)\r 5=Mini-RDIMM (width=TBD mm nom)\r 6=Mini-UDIMM (width=TBD mm nom)
04 = SDRAM Density and Banks\r b[3:0]:Total SDRAM capacity, in megabits 0=256Mb, 1=512Mb, 2=1Gb, 3=2Gb, 4=4Gb, 5=8Gb, 6=16Gb\r b[6:4]:Bank Address Bits 0=3 (8 banks), 1=4 (16 banks), 2=5 (32 banks), 3=6 (64 banks)
05 = SDRAM Addressing\r b[2:0]:Column Address Bits 0=9, 1=10, 2=11, 3=12\r b[5:3]:Row Address Bits 0=12, 1=13, 2=14, 3=15, 4=16
06 = Reserved
07 = Module Organization\r b[2:0]:SDRAM Device Width 0=4 bits, 1=8 bits, 2=16 bits, 3=32 bits\r b[5:3]:Number of Ranks 0=1 Rank, 1=2 Ranks, 2=3 Ranks, 3=4 Ranks
08 = Module Memory Bus Width\r b[2:0]:Primary bus width, in bits 0=8 bits, 1=16 bits, 2=32 bits, 3=64 bits\r b[4:3]:Bus width extension, in bits 0=0 bits (no extension), 1=8 bits
09 = Fine Timebase (FTB) Dividend / Divisor\r b[3:0]:Fine Timebase (FTB) Divisor\r b[7:4]:Fine Timebase (FTB) Dividend\r example: Dividend=5, Divisor=2, FTB Timebase=2.5ps
0A = Medium Timebase (MTB) Dividend\r example: byte10 (Dividend)=1, byte11 (Divisor)=8, MTB Timebase=0.125ns
0B = Medium Timebase (MTB) Divisor\r example: byte10 (Dividend)=1, byte11 (Divisor)=8, MTB Timebase=0.125ns
0C = Minimum SDRAM Cycle Time (tCKmin), in MTB Units\r example: 20*MTB=0.125 -> 2.5ns (DDR3 400MHz), 15*MTB=0.125 -> 1.875ns (DDR3 533MHz), 12*MTB=0.125 -> 1.5ns (DDR3 667MHz), 10*MTB=0.125 -> 1.25ns (DDR3 800MHz)
0D = Reserved
0E = CAS Latencies Supported, Low Byte\r b0:CL=4, b1:CL=5, b2:CL=6, b3:CL=7, b4:CL=8, b5:CL=9, b6:CL=10, b7:CL=11
0F = CAS Latencies Supported, High Byte\r b0:CL=12, b1:CL=13, b2:CL=14, b3:CL=15, b4:CL=16, b5:CL=17, b6:CL=18, b7:CL=reserved
10 = Minimum CAS Latency Time (tAAmin), in MTB Units
11 = Minimum Write Recovery Time (tWRmin), in MTB Units
12 = Minimum RAS# to CAS# Delay Time (tRCDmin), in MTB Units
13 = Minimum Row Active to Row Active Delay Time (tRRDmin), in MTB Units
14 = Minimum Row Precharge Delay Time (tRPmin), in MTB Units
15 = Upper Nibbles for tRAS and tRC, in MTB Units
16 = Minimum Active to Precharge Delay Time (tRASmin), Least Significant Byte, in MTB Units
17 = Minimum Active to Active/Refresh Delay Time (tRCmin), Least Significant Byte, in MTB Units
18 = Minimum Refresh Recovery Delay Time (tRFCmin), Least Significant Byte, in MTB Units
19 = Minimum Refresh Recovery Delay Time (tRFCmin), Most Significant Byte, in MTB Units
1A = Minimum Internal Write to Read Command Delay Time (tWTRmin), in MTB Units
1B = Minimum Internal Read to Precharge Command Delay Time (tRTPmin), in MTB Units
1C = Upper Nibble for tFAW\r b[3:0]=tFAW Most Significant Nibble\r b[7:4]=reserved
1D = Minimum Four Activate Window Delay Time (tFAWmin), Least Significant Byte, in MTB Units
1E = SDRAM Output Drivers Supported\r b0:RZQ/6 0=Not supported, 1=Supported\r b1:RZQ/7 0=Not supported, 1=Supported
1F = SDRAM Thermal and Refresh Options
20 = Reserved, General Section: Bytes 32-59
21 = Reserved, General Section: Bytes 32-59
22 = Reserved, General Section: Bytes 32-59
23 = Reserved, General Section: Bytes 32-59
24 = Reserved, General Section: Bytes 32-59
25 = Reserved, General Section: Bytes 32-59
26 = Reserved, General Section: Bytes 32-59
27 = Reserved, General Section: Bytes 32-59
28 = Reserved, General Section: Bytes 32-59
29 = Reserved, General Section: Bytes 32-59
2A = Reserved, General Section: Bytes 32-59
2B = Reserved, General Section: Bytes 32-59
2C = Reserved, General Section: Bytes 32-59
2D = Reserved, General Section: Bytes 32-59
2E = Reserved, General Section: Bytes 32-59
2F = Reserved, General Section: Bytes 32-59
30 = Reserved, General Section: Bytes 32-59
31 = Reserved, General Section: Bytes 32-59
32 = Reserved, General Section: Bytes 32-59
33 = Reserved, General Section: Bytes 32-59
34 = Reserved, General Section: Bytes 32-59
35 = Reserved, General Section: Bytes 32-59
36 = Reserved, General Section: Bytes 32-59
37 = Reserved, General Section: Bytes 32-59
38 = Reserved, General Section: Bytes 32-59
39 = Reserved, General Section: Bytes 32-59
3A = Reserved, General Section: Bytes 32-59
3B = Reserved, General Section: Bytes 32-59
3C = Module-Specific Section: Bytes 60-116
3D = Module-Specific Section: Bytes 60-116
3E = Module-Specific Section: Bytes 60-116
3F = Module-Specific Section: Bytes 60-116
40 = Module-Specific Section: Bytes 60-116
41 = Module-Specific Section: Bytes 60-116
42 = Module-Specific Section: Bytes 60-116
43 = Module-Specific Section: Bytes 60-116
44 = Module-Specific Section: Bytes 60-116
45 = Module-Specific Section: Bytes 60-116
46 = Module-Specific Section: Bytes 60-116
47 = Module-Specific Section: Bytes 60-116
48 = Module-Specific Section: Bytes 60-116
49 = Module-Specific Section: Bytes 60-116
4A = Module-Specific Section: Bytes 60-116
4B = Module-Specific Section: Bytes 60-116
4C = Module-Specific Section: Bytes 60-116
4D = Module-Specific Section: Bytes 60-116
4E = Module-Specific Section: Bytes 60-116
4F = Module-Specific Section: Bytes 60-116
50 = Module-Specific Section: Bytes 60-116
51 = Module-Specific Section: Bytes 60-116
52 = Module-Specific Section: Bytes 60-116
53 = Module-Specific Section: Bytes 60-116
54 = Module-Specific Section: Bytes 60-116
55 = Module-Specific Section: Bytes 60-116
56 = Module-Specific Section: Bytes 60-116
57 = Module-Specific Section: Bytes 60-116
58 = Module-Specific Section: Bytes 60-116
59 = Module-Specific Section: Bytes 60-116
5A = Module-Specific Section: Bytes 60-116
5B = Module-Specific Section: Bytes 60-116
5C = Module-Specific Section: Bytes 60-116
5D = Module-Specific Section: Bytes 60-116
5E = Module-Specific Section: Bytes 60-116
5F = Module-Specific Section: Bytes 60-116
60 = Module-Specific Section: Bytes 60-116
61 = Module-Specific Section: Bytes 60-116
62 = Module-Specific Section: Bytes 60-116
63 = Module-Specific Section: Bytes 60-116
64 = Module-Specific Section: Bytes 60-116
65 = Module-Specific Section: Bytes 60-116
66 = Module-Specific Section: Bytes 60-116
67 = Module-Specific Section: Bytes 60-116
68 = Module-Specific Section: Bytes 60-116
69 = Module-Specific Section: Bytes 60-116
6A = Module-Specific Section: Bytes 60-116
6B = Module-Specific Section: Bytes 60-116
6C = Module-Specific Section: Bytes 60-116
6D = Module-Specific Section: Bytes 60-116
6E = Module-Specific Section: Bytes 60-116
6F = Module-Specific Section: Bytes 60-116
70 = Module-Specific Section: Bytes 60-116
71 = Module-Specific Section: Bytes 60-116
72 = Module-Specific Section: Bytes 60-116
73 = Module-Specific Section: Bytes 60-116
74 = Module-Specific Section: Bytes 60-116
75 = Module Manufacturer ID Code, Least Significant Byte
76 = Module Manufacturer ID Code, Most Significant Byte
77 = Module Manufacturing Location
78 = Module Manufacturing Date
79 = Module Manufacturing Date
7A = Module Serial Number, Bytes 122-125
7B = Module Serial Number, Bytes 122-125
7C = Module Serial Number, Bytes 122-125
7D = Module Serial Number, Bytes 122-125
7E = SPD Cyclical Redundancy Code (CRC): Bytes 126-127
7F = SPD Cyclical Redundancy Code (CRC): Bytes 126-127
80 = Module Part Number, Bytes 128-145
81 = Module Part Number, Bytes 128-145
82 = Module Part Number, Bytes 128-145
83 = Module Part Number, Bytes 128-145
84 = Module Part Number, Bytes 128-145
85 = Module Part Number, Bytes 128-145
86 = Module Part Number, Bytes 128-145
87 = Module Part Number, Bytes 128-145
88 = Module Part Number, Bytes 128-145
89 = Module Part Number, Bytes 128-145
8A = Module Part Number, Bytes 128-145
8B = Module Part Number, Bytes 128-145
8C = Module Part Number, Bytes 128-145
8D = Module Part Number, Bytes 128-145
8E = Module Part Number, Bytes 128-145
8F = Module Part Number, Bytes 128-145
90 = Module Part Number, Bytes 128-145
91 = Module Part Number, Bytes 128-145
92 = Module Revision Code
93 = Module Revision Code
94 = DRAM Manufacturer ID Code, Least Significant Byte
95 = DRAM Manufacturer ID Code, Most Significant Byte
96 = Manufacturer's Specific Data, Bytes 150-175
97 = Manufacturer's Specific Data, Bytes 150-175
98 = Manufacturer's Specific Data, Bytes 150-175
99 = Manufacturer's Specific Data, Bytes 150-175
9A = Manufacturer's Specific Data, Bytes 150-175
9B = Manufacturer's Specific Data, Bytes 150-175
9C = Manufacturer's Specific Data, Bytes 150-175
9D = Manufacturer's Specific Data, Bytes 150-175
9E = Manufacturer's Specific Data, Bytes 150-175
9F = Manufacturer's Specific Data, Bytes 150-175
A0 = Manufacturer's Specific Data, Bytes 150-175
A1 = Manufacturer's Specific Data, Bytes 150-175
A2 = Manufacturer's Specific Data, Bytes 150-175
A3 = Manufacturer's Specific Data, Bytes 150-175
A4 = Manufacturer's Specific Data, Bytes 150-175
A5 = Manufacturer's Specific Data, Bytes 150-175
A6 = Manufacturer's Specific Data, Bytes 150-175
A7 = Manufacturer's Specific Data, Bytes 150-175
A8 = Manufacturer's Specific Data, Bytes 150-175
A9 = Manufacturer's Specific Data, Bytes 150-175
AA = Manufacturer's Specific Data, Bytes 150-175
AB = Manufacturer's Specific Data, Bytes 150-175
AC = Manufacturer's Specific Data, Bytes 150-175
AD = Manufacturer's Specific Data, Bytes 150-175
AE = Manufacturer's Specific Data, Bytes 150-175
AF = Manufacturer's Specific Data, Bytes 150-175
B0 = Open for Customer Use, Bytes 176-255
B1 = Open for Customer Use, Bytes 176-255
B2 = Open for Customer Use, Bytes 176-255
B3 = Open for Customer Use, Bytes 176-255
B4 = Open for Customer Use, Bytes 176-255
B5 = Open for Customer Use, Bytes 176-255
B6 = Open for Customer Use, Bytes 176-255
B7 = Open for Customer Use, Bytes 176-255
B8 = Open for Customer Use, Bytes 176-255
B9 = Open for Customer Use, Bytes 176-255
BA = Open for Customer Use, Bytes 176-255
BB = Open for Customer Use, Bytes 176-255
BC = Open for Customer Use, Bytes 176-255
BD = Open for Customer Use, Bytes 176-255
BE = Open for Customer Use, Bytes 176-255
BF = Open for Customer Use, Bytes 176-255
C0 = Open for Customer Use, Bytes 176-255
C1 = Open for Customer Use, Bytes 176-255
C2 = Open for Customer Use, Bytes 176-255
C3 = Open for Customer Use, Bytes 176-255
C4 = Open for Customer Use, Bytes 176-255
C5 = Open for Customer Use, Bytes 176-255
C6 = Open for Customer Use, Bytes 176-255
C7 = Open for Customer Use, Bytes 176-255
C8 = Open for Customer Use, Bytes 176-255
C9 = Open for Customer Use, Bytes 176-255
CA = Open for Customer Use, Bytes 176-255
CB = Open for Customer Use, Bytes 176-255
CC = Open for Customer Use, Bytes 176-255
CD = Open for Customer Use, Bytes 176-255
CE = Open for Customer Use, Bytes 176-255
CF = Open for Customer Use, Bytes 176-255
D0 = Open for Customer Use, Bytes 176-255
D1 = Open for Customer Use, Bytes 176-255
D2 = Open for Customer Use, Bytes 176-255
D3 = Open for Customer Use, Bytes 176-255
D4 = Open for Customer Use, Bytes 176-255
D5 = Open for Customer Use, Bytes 176-255
D6 = Open for Customer Use, Bytes 176-255
D7 = Open for Customer Use, Bytes 176-255
D8 = Open for Customer Use, Bytes 176-255
D9 = Open for Customer Use, Bytes 176-255
DA = Open for Customer Use, Bytes 176-255
DB = Open for Customer Use, Bytes 176-255
DC = Open for Customer Use, Bytes 176-255
DD = Open for Customer Use, Bytes 176-255
DE = Open for Customer Use, Bytes 176-255
DF = Open for Customer Use, Bytes 176-255
E0 = Open for Customer Use, Bytes 176-255
E1 = Open for Customer Use, Bytes 176-255
E2 = Open for Customer Use, Bytes 176-255
E3 = Open for Customer Use, Bytes 176-255
E4 = Open for Customer Use, Bytes 176-255
E5 = Open for Customer Use, Bytes 176-255
E6 = Open for Customer Use, Bytes 176-255
E7 = Open for Customer Use, Bytes 176-255
E8 = Open for Customer Use, Bytes 176-255
E9 = Open for Customer Use, Bytes 176-255
EA = Open for Customer Use, Bytes 176-255
EB = Open for Customer Use, Bytes 176-255
EC = Open for Customer Use, Bytes 176-255
ED = Open for Customer Use, Bytes 176-255
EE = Open for Customer Use, Bytes 176-255
EF = Open for Customer Use, Bytes 176-255
F0 = Open for Customer Use, Bytes 176-255
F1 = Open for Customer Use, Bytes 176-255
F2 = Open for Customer Use, Bytes 176-255
F3 = Open for Customer Use, Bytes 176-255
F4 = Open for Customer Use, Bytes 176-255
F5 = Open for Customer Use, Bytes 176-255
F6 = Open for Customer Use, Bytes 176-255
F7 = Open for Customer Use, Bytes 176-255
F8 = Open for Customer Use, Bytes 176-255
F9 = Open for Customer Use, Bytes 176-255
FA = Open for Customer Use, Bytes 176-255
FB = Open for Customer Use, Bytes 176-255
FC = Open for Customer Use, Bytes 176-255
FD = Open for Customer Use, Bytes 176-255
FE = Open for Customer Use, Bytes 176-255
FF = Open for Customer Use, Bytes 176-255

130
Tools/RwPortableX64V1.6.7/Win64/Portable/DDRSPD.IRW Normal file
View File

@@ -0,0 +1,130 @@
[INFO]
Name = DDR SDRAM SPD
00 = Number of Serial PD bytes written during module manufacturer\r 01 = 1 byte\r 02 = 2 bytes\r 03 = 3 bytes\r . .\r . .\r 80 = 128 bytes\r . .
01 = Total number of bytes in Serial PD device\r 01 = 2 bytes\r 02 = 4 bytes\r 03 = 8 bytes\r . .\r . .\r 07 = 128 bytes\r 08 = 256 bytes\r . .
02 = Fundamental memory type\r 01 = FPM\r 02 = EDO\r 03 = Pipelined Nibble\r 04 = SDR SDRAM\r 05 = ROM\r 06 = DDR SGRAM\r 07 = DDR SDRAM
03 = Number of row addresses (includes Mixed-size Row addr) This field describes the Row addressing on the module. If there is one physical bank on the module or if there are two physical banks of the same size and organization, then bits 0-3 are used to represent the number of row addresses for each physical bank. If the module has two physical banks of asymmetric size, then bits 0-3 represent the number of row addresses for physical bank 1 and bits 4-7 represent the number of row addresses for physical bank 2 (bank 2 device is 2x bank 1 device width).
04 = Number of column addresses (includes Mixed-size Col addr) This field describes the Column addressing on the module. If there is one physical bank on the module or if there are two physical banks of the same size, then bits 0-3 are used to represent the number of column addresses for each physical bank. If the module has two physical banks of asymmetric size, then bits 0-3 represent the number of column addresses for physical bank 1 and bits 4-7 represent the number of column addresses for physical bank 2 (bank 2 device is 2x bank 1 device width).
05 = Number of physical banks on DIMM
06 = Module Data Width, Bytes 6 and 7 are used to designate the module<6C><65>s data width. The data width is presented as a 16-bit word: bit 0 of byte 6 becomes the LSB of the 16 bit width identifier and bit 7 of byte 7 becomes the MSB. Consequently, if the module has a width of less than 255 bits, byte 7 will be 00h. If the data width is 256 bits or more, byte 7 is used in conjunction with byte 6 to designate the total module width.
07 = Module Data Width, Bytes 6 and 7 are used to designate the module<6C><65>s data width. The data width is presented as a 16-bit word: bit 0 of byte 6 becomes the LSB of the 16 bit width identifier and bit 7 of byte 7 becomes the MSB. Consequently, if the module has a width of less than 255 bits, byte 7 will be 00h. If the data width is 256 bits or more, byte 7 is used in conjunction with byte 6 to designate the total module width.
08 = Voltage Interface Level of this assembly\r 0 = TTL/5V tolerant\r 1 = 1 LVTTL (not 5V tolerant)\r 2 = HSTL 1.5V\r 3 = SSTL 3.3V\r 4 = SSTL 2.5V
09 = SDRAM Cycle time, CL=X (highest CAS latency), This byte defines the minimum cycle time for the SDRAM device at the highest CAS Latency, CAS Latency=X, defined in byte 18. Byte 9, Cycle time for CAS Latency=X, is split into two nibbles: the higher order nibble (bits 4-7) designates the cycle time to a granularity of 1ns; the value presented by the lower order nibble (bits 0-3) has a granularity of .1ns and is added to the value designated by the higher nibble.
0A = SDRAM Access from Clock (highest CAS latency), This byte defines the maximum clock to data out time () for the SDRAM device. This is the Clock to data out specification at the highest given CAS Latency specified in byte 18 of this SPD specification. The byte is split into two nibbles: the higher order nibble (bits 4-7) designate the access time to a granularity of 0.1ns; the value presented by the lower order nibble (bits 0-3) has the granularity of .01ns and is added to the value designated by the higher nibble.
0B = DIMM configuration type, This byte describes the module's error detection and/or correction scheme.\r 0 = None\r 1 = Parity\r 2 = ECC
0C = Refresh Rate/Type\r 00 = Normal (15.625 us)\r 01 = Reduced (.25x) 3.9us\r 02 = Reduced (.5x) 7.8us\r 03 = Extended (2x) 31.3us\r 04 = Extended (4x) 62.5us\r 05 = Extended (8x) 125us\rSelf Refresh Entries\r 80 = Normal (15.625 us)\r 81 = Reduced (.25x) 3.9us\r 82 = Reduced (.5x) 7.8us\r 83 = Extended (2x) 31.3us\r 84 = Extended (4x) 62.5us\r 85 = Extended (8x) 125us
0D = Primary SDRAM Width, B6:0 = width of the primary data SDRAM. B7 = 1 - when there is a second physical bank on the module which is of different size from the first physical bank (the second physical bank's data RAMs are 2X the width of those on the first physical bank). If there is a second physical bank of the same size and configuration as the first, then bit 7 remains as 0 and primary SDRAM width for both banks is expressed using bits 0-6.
0E = Error Checking SDRAM width, If the module incorporates error checking and if the primary data SDRAM does not include these bits - i.e. there are separate error checking SDRAMs <20>X then the error checking SDRAM<41><4D>s width is expressed in this byte. B6:0 = Error checking SDRAM<41><4D>s width. B7 = 1 - when the module has a second physical bank that is a different size than the first physical bank. Bit 7 set to 1 indicates that Bank 2's error checking RAMs are 2X the width of those on the first physical bank.
0F = SDRAM Device Attributes <20>V Minimum Clock Delay, Back-to-Back Random Column Access
10 = Burst Lengths Supported. This byte describes which various programmable burst lengths are supported by the devices on the module. If the bit is 1, then that Burst Length is supported on the module; if the bit is 0, then that Burst Length is not supported by the module.
11 = SDRAM Device Attributes <20>V Number of Banks on SDRAM Device
12 = CAS# Latencies Supported. This byte describes which of the programmable CAS latencies (CAS to data out) are acceptable for the SDRAM devices used on the module.\r B0 = 1\r B1 = 1.5\r B2 = 2\r B3 = 2.5\r B4 = 3\r B5 = 3.5
13 = CS# Latency. Tthis byte defines the Chip Select (CS) latency associated with the SDRAM devices used on the module.\r B0 = 0\r B1 = 1\r B2 = 2\r B3 = 3\r B4 = 4\r B5 = 5\r B6 = 6
14 = Write Latency. This byte defines the write (W) latency associated with the SDRAM devices used on the module.\r B0 = 0\r B1 = 1\r B2 = 2\r B3 = 3
15 = SDRAM Module Attributes
16 = SDRAM Device Attributes
17 = Minimum SDRAM Cycle time at CL X-0.5 (2nd highest CAS latency)
18 = Maximum Data Access Time (tAC) from Clock at CLX-0.5 (2nd highest CAS latency)
19 = Minimum Clock Cycle at CLX-1 (3rd highest CAS latency)
1A = SDRAM Device Maximum Data Access Time (tAC) from Clock at CLX-1 (3rd highest CAS latency)
1B = Minimum Row Precharge Time (tRP), the higher order bits (bits 2-7) designate the time to a granularity of 1ns; the value presented by the lower order bits (bits 0-1) has a granularity of .25ns and is added to the value designated by the higher bits.
1C = Minimum Row Active to Row Active delay (tRRD), the higher order bits (bits 2-7) designate the time to a granularity of 1ns; the value presented by the lower order bits (bits 0-1) has a granularity of .25ns and is added to the value designated by the higher bits.
1D = Minimum RAS to CAS delay (tRCD), the higher order bits (bits 2-7) designate the time to a granularity of 1ns; the value presented by the lower order bits (bits 0-1) has a granularity of .25ns and is added to the value designated by the higher bits.
1E = Minimum Active to Precharge Time (tRAS), This byte identifies the minimum active to precharge time.
1F = Density of each row on module (mixed, non-mixed sizes), This byte describes the density of each physical bank on the SRAM DIMM. This byte will have at least one bit set to 1 to represent at least one bank's density. If there are more than one physical bank on the module (as represented in byte 5), and they have the same density, then only one bit is set in this field. If the module has more than one physical bank of different sizes, then more than one bit will be set; each bit set for each density represented.
20 = Address and Command Input Setup Time Before Clock, This field describes the input setup time before the rising edge of the clock at the SDRAM device on unbuffered modules, or at the register on registered modules. The byte is split into two nibbles: the higher order nibble (bits 4-7) designate the access time to a granularity of 0.1ns; the value presented by the lower order nibble (bits 0-3) has the granularity of .01ns and is added to the value designated by the higher nibble.
21 = Address and Command Input Hold Time After Clock, This field describes the input hold time after the rising edge of the clock at the SDRAM device on unbuffered modules, or at the register on registered modules. The byte is split into two nibbles: the higher order nibble (bits 4-7) designate the access time to a granularity of 0.1ns; the value presented by the lower order nibble (bits 0-3) has the granularity of .01ns and is added to the value designated by the higher nibble.
22 = Device Data/Data Mask Input Setup Time Before Data Strobe, This field describes the input setup time before the rising or falling edge of the Data Strobe. The byte is split into two nibbles: the higher order nibble (bits 4-7) designates the time to a granularity of 0.1ns; the value presented by the lower order nibble (bits 0-3) has the granularity of .01ns and is added to the value designated by the higher nibble.
23 = Device Data/Data Mask Input Hold Time After Data Strobe, This field describes the input hold time after the rising or falling edge of the Data Strobe. The byte is split into two nibbles: the higher order nibble (bits 4-7) designates the time to a granularity of 0.1ns; the value presented by the lower order nibble (bits 0-3) has the granularity of .01ns and is added to the value designated by the higher nibble.
24 = Reserved for VCSDRAM
25 = Reserved for VCSDRAM
26 = Reserved for VCSDRAM
27 = Reserved for VCSDRAM
28 = Reserved for VCSDRAM
29 = SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC), This byte identifies the minimum active to active or auto refresh time.
2A = SDRAM Device Minimum Auto<74>VRefresh to Active/Auto<74>VRefresh (tRFC), This byte identifies the minimum Auto-refresh to Active/Auto-Refresh command period.
2B = SDRAM Device Maximum device cycle time (tCKmax), This byte identifies the maximum device cycle time at any CAS latency, in nanoseconds. one special reserved value, FF, is used to describe devices which have no maximum cycle time. This byte split into two pieces: the higher order bits (bits 2-7) designate the time to a granularity of 1ns; the value presented by the lower order bits (bits 0-1) has a granularity of .25ns and is added to the value designated by the higher bits.
2C = SDRAM Device Maximum skew between DQS and DQ signals (tDQSQ), This byte identifies the maximum skew between DQS and associated DQ signals for each device, in hundredths of nanoseconds.
2D = DDR SDRAM Device Maximum Read DataHold Skew Factor (tQHS), This byte identifies the maximum skew factor used in the calculation of read data hold time from edges of DQS, specifically tQH = tHP - tQHS where tQHS is the read data hold skew factor. This SPD byte is split into two nibbles: the higher order nibble (bits 4-7) designate the access time to a granulartiy of 0.01 ns; the value presented by the lower order nibble (bits 0-3) has the granularity of 0.01ns and is added to the value designated by the higher nibble.
2E = Superset information (may be used in future)
2F = Superset information (may be used in future)
30 = Superset information (may be used in future)
31 = Superset information (may be used in future)
32 = Superset information (may be used in future)
33 = Superset information (may be used in future)
34 = Superset information (may be used in future)
35 = Superset information (may be used in future)
36 = Superset information (may be used in future)
37 = Superset information (may be used in future)
38 = Superset information (may be used in future)
39 = Superset information (may be used in future)
3A = Superset information (may be used in future)
3B = Superset information (may be used in future)
3C = Superset information (may be used in future)
3D = Superset information (may be used in future)
3E = SPD Revision
3F = Checksum for Bytes 0-62 (00h - 3Eh)
40 = Manufacturer's JEDEC ID code per JEP-108E
41 = Manufacturer's JEDEC ID code per JEP-108E
42 = Manufacturer's JEDEC ID code per JEP-108E
43 = Manufacturer's JEDEC ID code per JEP-108E
44 = Manufacturer's JEDEC ID code per JEP-108E
45 = Manufacturer's JEDEC ID code per JEP-108E
46 = Manufacturer's JEDEC ID code per JEP-108E
47 = Manufacturer's JEDEC ID code per JEP-108E
48 = Manufacturing Location
49 = Manufacturer's Part Number
4A = Manufacturer's Part Number
4B = Manufacturer's Part Number
4C = Manufacturer's Part Number
4D = Manufacturer's Part Number
4E = Manufacturer's Part Number
4F = Manufacturer's Part Number
50 = Manufacturer's Part Number
51 = Manufacturer's Part Number
52 = Manufacturer's Part Number
53 = Manufacturer's Part Number
54 = Manufacturer's Part Number
55 = Manufacturer's Part Number
56 = Manufacturer's Part Number
57 = Manufacturer's Part Number
58 = Manufacturer's Part Number
59 = Manufacturer's Part Number
5A = Manufacturer's Part Number
5B = Revision Code
5C = Revision Code
5D = Manufacturing Date
5E = Manufacturing Date
5F = Assembly Serial Number
60 = Assembly Serial Number
61 = Assembly Serial Number
62 = Assembly Serial Number
63 = Manufacturer Specific Data
64 = Manufacturer Specific Data
65 = Manufacturer Specific Data
66 = Manufacturer Specific Data
67 = Manufacturer Specific Data
68 = Manufacturer Specific Data
69 = Manufacturer Specific Data
6A = Manufacturer Specific Data
6B = Manufacturer Specific Data
6C = Manufacturer Specific Data
6D = Manufacturer Specific Data
6E = Manufacturer Specific Data
6F = Manufacturer Specific Data
70 = Manufacturer Specific Data
71 = Manufacturer Specific Data
72 = Manufacturer Specific Data
73 = Manufacturer Specific Data
74 = Manufacturer Specific Data
75 = Manufacturer Specific Data
76 = Manufacturer Specific Data
77 = Manufacturer Specific Data
78 = Manufacturer Specific Data
79 = Manufacturer Specific Data
7A = Manufacturer Specific Data
7B = Manufacturer Specific Data
7C = Manufacturer Specific Data
7D = Manufacturer Specific Data
7E = Intel specification frequency
7F = Intel Specification CAS# Latency support

65
Tools/RwPortableX64V1.6.7/Win64/Portable/PCIBRI.IRW Normal file
View File

@@ -0,0 +1,65 @@
[INFO]
00 = Vendor ID - Offset [1:0]\r\rThe Vendor ID register identifies the manufacturer of the device and is assigned by PCISIG to insure uniqueness.
01 = Vendor ID - Offset [1:0]\r\rThe Vendor ID register identifies the manufacturer of the device and is assigned by PCISIG to insure uniqueness.
02 = Device ID - Offset [3:2]\r\rThe Device ID register identifies the particular device and is assigned by the vendor.
03 = Device ID - Offset [3:2]\r\rThe Device ID register identifies the particular device and is assigned by the vendor.
04 = Command - Offset [5:4]\r B0 - I/O Space Enable\r B1 - Memory Space Enable\r B2 - Bus Master Enable\r B3 - Special Cycle Enable\r B4 - Memory Write and Invalidate\r B5 - VGA Palette Snoop Enable\r B6 - Parity Error Response\r B7 - Reserved\r B8 - SERR# Enable\r B9 - Fast Back-to-Back Enable\r B10 - Interrupt Disable\r B15:11 - Reserved
05 = Command - Offset [5:4]\r B0 - I/O Space Enable\r B1 - Memory Space Enable\r B2 - Bus Master Enable\r B3 - Special Cycle Enable\r B4 - Memory Write and Invalidate\r B5 - VGA Palette Snoop Enable\r B6 - Parity Error Response\r B7 - Reserved\r B8 - SERR# Enable\r B9 - Fast Back-to-Back Enable\r B10 - Interrupt Disable\r B15:11 - Reserved
06 = Status - Offset [7:6]\r B2:0 - Reserved\r B3 - Interrupt Status\r B4 - Capabilities List\r B5 - 66 MHz Capable\r B6 - Reserved\r B7 - Fast Back-to-Back Capable\r B8 - Master Data Parity Error\r B10:9 - DEVSEL# Timing\r 00 - fast\r 01 - medium\r 02 - slow\r B11 - Signaled Target-Abort\r B12 - Received Target-Abort\r B13 - Received Master-Abort\r B14 - Signaled System Error\r B15 - Detected Parity Error
07 = Status - Offset [7:6]\r B2:0 - Reserved\r B3 - Interrupt Status\r B4 - Capabilities List\r B5 - 66 MHz Capable\r B6 - Reserved\r B7 - Fast Back-to-Back Capable\r B8 - Master Data Parity Error\r B10:9 - DEVSEL# Timing\r 00 - fast\r 01 - medium\r 02 - slow\r B11 - Signaled Target-Abort\r B12 - Received Target-Abort\r B13 - Received Master-Abort\r B14 - Signaled System Error\r B15 - Detected Parity Error
08 = Revision ID\r\rThe Revision ID register specifies a device-specific revision identifier.
09 = Class code - Programming Interface type\r\rThe Class Code register is used to identify the function of the device.
0A = Class code - Sub type\r\rThe Class Code register is used to identify the function of the device.
0B = Class code - Base type\r\rThe Class Code register is used to identify the function of the device.
0C = Cache line size\r\rThe Cacheline Size register is used when terminating a transaction that uses the Memory Write and Invalidate command and when prefetching (Memory Read Line and Memory Read Multiple commands).
0D = Primary Latency timer\r\rThe Latency Timer register is required if a bridge is capable of a burst transfer of more than two data phases on its primary interface.
0E = Header type\r 00 - Standard PCI\r 01 - PCI-to-PCI Bridge\r 02 - Cardbus\r B7 = 1 - Multi-Function Device
0F = Built-In Self Test\r B3:0 - BIST Result\r B5:4 - Reserved\r B6 - Start BIST\r B7 - BIST Capable
10 = Base Address 0 - Offset [13:10]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
11 = Base Address 0 - Offset [13:10]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
12 = Base Address 0 - Offset [13:10]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
13 = Base Address 0 - Offset [13:10]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
14 = Base Address 1 - Offset [17:14]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
15 = Base Address 1 - Offset [17:14]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
16 = Base Address 1 - Offset [17:14]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
17 = Base Address 1 - Offset [17:14]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
18 = Primary bus number\r\rThe Primary Bus Number register is used to record the bus number of the PCI bus segment to which the primary interface of the bridge is connected.
19 = Secondary bus number\r\rThe Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected.
1A = Subordinate bus number\r\rThe Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge.
1B = Secondary latency timer\r\rThe Latency Timer register is required if a bridge is capable of a burst transfer of more than two data phases on its secondary interface.
1C = I/O base\r\rThe I/O Base and I/O Limit registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to the other.\r\r B3:0 - I/O Addressing Capability\r 00 - 16-bit I/O addressing\r 01 - 32-bit I/O addressing\r 02-0F - Reserved\r B7:4 - I/O base AD[15:12]\r AD[11:0] = 000
1D = I/O limit\r\rThe I/O Base and I/O Limit registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to the other.\r\r B3:0 - I/O Addressing Capability\r 00 - 16-bit I/O addressing\r 01 - 32-bit I/O addressing\r 02-0F - Reserved\r B7:4 - I/O limit AD[15:12]\r AD[11:0] = FFF
1E = Secondary status - Offset [1F:1E]\r B4:0 - Reserved\r B5 - 66 MHz Capable\r B6 - Reserved\r B7 - Fast Back-to-Back Capable\r B8 - Master Data Parity Error\r B10:9 - DEVSEL# Timing\r 00 - fast\r 01 - medium\r 02 - slow\r B11 - Signaled Target-Abort\r B12 - Received Target-Abort\r B13 - Received Master-Abort\r B14 - Signaled System Error\r B15 - Detected Parity Error
1F = Secondary status - Offset [1F:1E]\r B4:0 - Reserved\r B5 - 66 MHz Capable\r B6 - Reserved\r B7 - Fast Back-to-Back Capable\r B8 - Master Data Parity Error\r B10:9 - DEVSEL# Timing\r 00 - fast\r 01 - medium\r 02 - slow\r B11 - Signaled Target-Abort\r B12 - Received Target-Abort\r B13 - Received Master-Abort\r B14 - Signaled System Error\r B15 - Detected Parity Error
20 = Memory base - Offset [21:20]\r\rThe Memory Base and Memory Limit registers are both required registers that define a memory mapped I/O address range which is used by the bridge to determine when to forward memory transactions from one interface to the other.\r\r B3:0 - Reserved\r B15:4 - Memory base AD[31:20]\r AD[19:0] = 00000
21 = Memory base - Offset [21:20]\r\rThe Memory Base and Memory Limit registers are both required registers that define a memory mapped I/O address range which is used by the bridge to determine when to forward memory transactions from one interface to the other.\r\r B3:0 - Reserved\r B15:4 - Memory base AD[31:20]\r AD[19:0] = 00000
22 = Memory limit - Offset [23:22]\r\rThe Memory Base and Memory Limit registers are both required registers that define a memory mapped I/O address range which is used by the bridge to determine when to forward memory transactions from one interface to the other.\r\r B3:0 - Reserved\r B15:4 - Memory limit AD[31:20]\r AD[19:0] = FFFFF
23 = Memory limit - Offset [23:22]\r\rThe Memory Base and Memory Limit registers are both required registers that define a memory mapped I/O address range which is used by the bridge to determine when to forward memory transactions from one interface to the other.\r\r B3:0 - Reserved\r B15:4 - Memory limit AD[31:20]\r AD[19:0] = FFFFF
24 = Prefetchable memory base\r - Offset [25:24]\r\rThe Prefetchable Memory Base and Prefetchable Memory Limit registers are optional. They define a prefetchable memory address range which is used by the bridge to determine when to forward memory transactions from one interface to the other.\r\r B3:0 - Reserved\r B15:4 - Memory base AD[31:20]\r AD[19:0] = 00000
25 = Prefetchable memory base\r - Offset [25:24]\r\rThe Prefetchable Memory Base and Prefetchable Memory Limit registers are optional. They define a prefetchable memory address range which is used by the bridge to determine when to forward memory transactions from one interface to the other.\r\r B3:0 - Reserved\r B15:4 - Memory base AD[31:20]\r AD[19:0] = 00000
26 = Prefetchable memory limit\r - Offset [27:26]\r\rThe Prefetchable Memory Base and Prefetchable Memory Limit registers are optional. They define a prefetchable memory address range which is used by the bridge to determine when to forward memory transactions from one interface to the other.\r\r B3:0 - Reserved\r B15:4 - Memory limit AD[31:20]\r AD[19:0] = FFFFF
27 = Prefetchable memory limit\r - Offset [27:26]\r\rThe Prefetchable Memory Base and Prefetchable Memory Limit registers are optional. They define a prefetchable memory address range which is used by the bridge to determine when to forward memory transactions from one interface to the other.\r\r B3:0 - Reserved\r B15:4 - Memory limit AD[31:20]\r AD[19:0] = FFFFF
28 = Prefetchable base upper 32 bits\r - Offset [2B:28]\r\rThe Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32 Bits registers are optional extensions to the Prefetchable Memory Base and Prefetchable Memory Limit registers.
29 = Prefetchable base upper 32 bits\r - Offset [2B:28]\r\rThe Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32 Bits registers are optional extensions to the Prefetchable Memory Base and Prefetchable Memory Limit registers.
2A = Prefetchable base upper 32 bits\r - Offset [2B:28]\r\rThe Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32 Bits registers are optional extensions to the Prefetchable Memory Base and Prefetchable Memory Limit registers.
2B = Prefetchable base upper 32 bits\r - Offset [2B:28]\r\rThe Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32 Bits registers are optional extensions to the Prefetchable Memory Base and Prefetchable Memory Limit registers.
2C = Prefetchable limit upper 32 bits\r - Offset [2F:2C]\r\rThe Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32 Bits registers are optional extensions to the Prefetchable Memory Base and Prefetchable Memory Limit registers.
2D = Prefetchable limit upper 32 bits\r - Offset [2F:2C]\r\rThe Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32 Bits registers are optional extensions to the Prefetchable Memory Base and Prefetchable Memory Limit registers.
2E = Prefetchable limit upper 32 bits\r - Offset [2F:2C]\r\rThe Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32 Bits registers are optional extensions to the Prefetchable Memory Base and Prefetchable Memory Limit registers.
2F = Prefetchable limit upper 32 bits\r - Offset [2F:2C]\r\rThe Prefetchable Base Upper 32 Bits and Prefetchable Limit Upper 32 Bits registers are optional extensions to the Prefetchable Memory Base and Prefetchable Memory Limit registers.
30 = I/O base upper 16 bits\r - Offset [31:30]\r\rThe I/O Base Upper 16 Bits and I/O Limit Upper 16 Bits registers are optional extensions to the I/O Base and I/O Limit registers. If the I/O Base and I/O Limit registers indicate support for 16-bit I/O address decoding, then these registers are implemented as read-only registers which return zero when read. If 32-bit I/O addressing is supported, then these registers must be initialized by configuration software so default states are not specified.
31 = I/O base upper 16 bits\r - Offset [31:30]\r\rThe I/O Base Upper 16 Bits and I/O Limit Upper 16 Bits registers are optional extensions to the I/O Base and I/O Limit registers. If the I/O Base and I/O Limit registers indicate support for 16-bit I/O address decoding, then these registers are implemented as read-only registers which return zero when read. If 32-bit I/O addressing is supported, then these registers must be initialized by configuration software so default states are not specified.
32 = I/O limit upper 16 bits\r - Offset [33:32]\r\rThe I/O Base Upper 16 Bits and I/O Limit Upper 16 Bits registers are optional extensions to the I/O Base and I/O Limit registers. If the I/O Base and I/O Limit registers indicate support for 16-bit I/O address decoding, then these registers are implemented as read-only registers which return zero when read. If 32-bit I/O addressing is supported, then these registers must be initialized by configuration software so default states are not specified.
33 = I/O limit upper 16 bits\r - Offset [33:32]\r\rThe I/O Base Upper 16 Bits and I/O Limit Upper 16 Bits registers are optional extensions to the I/O Base and I/O Limit registers. If the I/O Base and I/O Limit registers indicate support for 16-bit I/O address decoding, then these registers are implemented as read-only registers which return zero when read. If 32-bit I/O addressing is supported, then these registers must be initialized by configuration software so default states are not specified.
34 = Capabilities pointer\r\rThis optional register is used to point to a linked list of additional capabilities implemented by this device.
35 = Reserved - Offset [37:35]\r\rRead accesses to these registers must complete normally and return a value of zero after reset. However, if subsequently written, these registers may return an indeterminate value.
36 = Reserved - Offset [37:35]\r\rRead accesses to these registers must complete normally and return a value of zero after reset. However, if subsequently written, these registers may return an indeterminate value.
37 = Reserved - Offset [37:35]\r\rRead accesses to these registers must complete normally and return a value of zero after reset. However, if subsequently written, these registers may return an indeterminate value.
38 = Expansion ROM base Address\r - Offset [3B:38]\r B0 = 1 - Expansion ROM enabled\r B10:1 - Reserved\r B31:11 - base address
39 = Expansion ROM base Address\r - Offset [3B:38]\r B0 = 1 - Expansion ROM enabled\r B10:1 - Reserved\r B31:11 - base address
3A = Expansion ROM base Address\r - Offset [3B:38]\r B0 = 1 - Expansion ROM enabled\r B10:1 - Reserved\r B31:11 - base address
3B = Expansion ROM base Address\r - Offset [3B:38]\r B0 = 1 - Expansion ROM enabled\r B10:1 - Reserved\r B31:11 - base address
3C = Interrupt line\r\rThe Interrupt Line register is a read/write register used to communicate interrupt line routing information between initialization code and the device driver. This register must be initialized by initialization code so a default state is not specified. The value written to the Interrupt Line register specifies the routing of the device<63><65>s INTx# pin to the system interrupt controller.
3D = Interrupr pin\r\rThe Interrupt Pin register is used to indicate which interrupt pin the bridge uses. A value of 1 corresponds to INTA#; a value of 2 corresponds to INTB#; a value of 3 corresponds to INTC#; and a value of 4 corresponds to INTD#.
3E = Bridge control - Offset [3F:3E]\r B0 - Parity Error Response Enable\r B1 - SERR# Enable\r B2 - ISA Enable\r B3 - VGA Enable\r B4 - VGA 16-bit decode\r B5 - Master-Abort Mode\r B6 - Secondary Bus Reset\r B7 - Fast Back-to-Back Enable\r B8 - Primary Discard Timer\r B9 - Secondary Discard Timer\r B10 - Discard Timer Status\r B11 - Discard Timer SERR# Enable\r B15:12 - Reserved
3F = Bridge control - Offset [3F:3E]\r B0 - Parity Error Response Enable\r B1 - SERR# Enable\r B2 - ISA Enable\r B3 - VGA Enable\r B4 - VGA 16-bit decode\r B5 - Master-Abort Mode\r B6 - Secondary Bus Reset\r B7 - Fast Back-to-Back Enable\r B8 - Primary Discard Timer\r B9 - Secondary Discard Timer\r B10 - Discard Timer Status\r B11 - Discard Timer SERR# Enable\r B15:12 - Reserved

65
Tools/RwPortableX64V1.6.7/Win64/Portable/PCISTD.IRW Normal file
View File

@@ -0,0 +1,65 @@
[INFO]
00 = Vendor ID - Offset [1:0]\r\rThe Vendor ID register identifies the manufacturer of the device and is assigned by PCISIG to insure uniqueness.
01 = Vendor ID - Offset [1:0]\r\rThe Vendor ID register identifies the manufacturer of the device and is assigned by PCISIG to insure uniqueness.
02 = Device ID - Offset [3:2]\r\rThe Device ID register identifies the particular device and is assigned by the vendor.
03 = Device ID - Offset [3:2]\r\rThe Device ID register identifies the particular device and is assigned by the vendor.
04 = Command - Offset [5:4]\r B0 - I/O Space Enable\r B1 - Memory Space Enable\r B2 - Bus Master Enable\r B3 - Special Cycle Enable\r B4 - Memory Write and Invalidate\r B5 - VGA Palette Snoop Enable\r B6 - Parity Error Response\r B7 - Reserved\r B8 - SERR# Enable\r B9 - Fast Back-to-Back Enable\r B10 - Interrupt Disable\r B15:11 - Reserved
05 = Command - Offset [5:4]\r B0 - I/O Space Enable\r B1 - Memory Space Enable\r B2 - Bus Master Enable\r B3 - Special Cycle Enable\r B4 - Memory Write and Invalidate\r B5 - VGA Palette Snoop Enable\r B6 - Parity Error Response\r B7 - Reserved\r B8 - SERR# Enable\r B9 - Fast Back-to-Back Enable\r B10 - Interrupt Disable\r B15:11 - Reserved
06 = Status - Offset [7:6]\r B2:0 - Reserved\r B3 - Interrupt Status\r B4 - Capabilities List\r B5 - 66 MHz Capable\r B6 - Reserved\r B7 - Fast Back-to-Back Capable\r B8 - Master Data Parity Error\r B10:9 - DEVSEL# Timing\r 00 - fast\r 01 - medium\r 02 - slow\r B11 - Signaled Target-Abort\r B12 - Received Target-Abort\r B13 - Received Master-Abort\r B14 - Signaled System Error\r B15 - Detected Parity Error
07 = Status - Offset [7:6]\r B2:0 - Reserved\r B3 - Interrupt Status\r B4 - Capabilities List\r B5 - 66 MHz Capable\r B6 - Reserved\r B7 - Fast Back-to-Back Capable\r B8 - Master Data Parity Error\r B10:9 - DEVSEL# Timing\r 00 - fast\r 01 - medium\r 02 - slow\r B11 - Signaled Target-Abort\r B12 - Received Target-Abort\r B13 - Received Master-Abort\r B14 - Signaled System Error\r B15 - Detected Parity Error
08 = Revision ID\r\rThe Revision ID register specifies a device-specific revision identifier.
09 = Class code - Programming Interface type\r\rThe Class Code register is used to identify the function of the device.
0A = Class code - Sub type\r\rThe Class Code register is used to identify the function of the device.
0B = Class code - Base type\r\rThe Class Code register is used to identify the function of the device.
0C = Cache line size\r\rThe Cacheline Size register is used when terminating a transaction that uses the Memory Write and Invalidate command and when prefetching (Memory Read Line and Memory Read Multiple commands).
0D = Latency timer\r\rThe Latency Timer register is required if a bridge is capable of a burst transfer of more than two data phases on its primary interface.
0E = Header type\r 00 - Standard PCI\r 01 - PCI-to-PCI Bridge\r 02 - Cardbus\r B7 = 1 - Multi-Function Device
0F = Built-In Self Test\r B3:0 - BIST Result\r B5:4 - Reserved\r B6 - Start BIST\r B7 - BIST Capable
10 = Base Address 0 - Offset [13:10]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
11 = Base Address 0 - Offset [13:10]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
12 = Base Address 0 - Offset [13:10]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
13 = Base Address 0 - Offset [13:10]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
14 = Base Address 1 - Offset [17:14]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
15 = Base Address 1 - Offset [17:14]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
16 = Base Address 1 - Offset [17:14]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
17 = Base Address 1 - Offset [17:14]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
18 = Base Address 2 - Offset [1B:18]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
19 = Base Address 2 - Offset [1B:18]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
1A = Base Address 2 - Offset [1B:18]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
1B = Base Address 2 - Offset [1B:18]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
1C = Base Address 3 - Offset [1F:1C]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
1D = Base Address 3 - Offset [1F:1C]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
1E = Base Address 3 - Offset [1F:1C]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
1F = Base Address 3 - Offset [1F:1C]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
20 = Base Address 4 - Offset [23:20]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
21 = Base Address 4 - Offset [23:20]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
22 = Base Address 4 - Offset [23:20]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
23 = Base Address 4 - Offset [23:20]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
24 = Base Address 5 - Offset [27:24]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
25 = Base Address 5 - Offset [27:24]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
26 = Base Address 5 - Offset [27:24]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
27 = Base Address 5 - Offset [27:24]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
28 = Cardbus CIS pointer\r - Offset [2B:28]\r\rThis optional register is used by those devices that want to share silicon between CardBus and PCI. The field is used to point to the Card Information Structure (CIS) for the CardBus card.
29 = Cardbus CIS pointer\r - Offset [2B:28]\r\rThis optional register is used by those devices that want to share silicon between CardBus and PCI. The field is used to point to the Card Information Structure (CIS) for the CardBus card.
2A = Cardbus CIS pointer\r - Offset [2B:28]\r\rThis optional register is used by those devices that want to share silicon between CardBus and PCI. The field is used to point to the Card Information Structure (CIS) for the CardBus card.
2B = Cardbus CIS pointer\r - Offset [2B:28]\r\rThis optional register is used by those devices that want to share silicon between CardBus and PCI. The field is used to point to the Card Information Structure (CIS) for the CardBus card.
2C = Subsystem vendor ID\r - Offset [2D:2C]\r\rThese registers are used to uniquely identify the add-in card or subsystem where the PCI device resides. They provide a mechanism for add-in card vendors to distinguish their add-in cards from one another even though the add-in cards may have the same PCI controller on them (and, therefore, the same Vendor ID and Device ID).
2D = Subsystem vendor ID\r - Offset [2D:2C]\r\rThese registers are used to uniquely identify the add-in card or subsystem where the PCI device resides. They provide a mechanism for add-in card vendors to distinguish their add-in cards from one another even though the add-in cards may have the same PCI controller on them (and, therefore, the same Vendor ID and Device ID).
2E = Subsystem ID - Offset [2F:2E]\r\rThese registers are used to uniquely identify the add-in card or subsystem where the PCI device resides. They provide a mechanism for add-in card vendors to distinguish their add-in cards from one another even though the add-in cards may have the same PCI controller on them (and, therefore, the same Vendor ID and Device ID).
2F = Subsystem ID - Offset [2F:2E]\r\rThese registers are used to uniquely identify the add-in card or subsystem where the PCI device resides. They provide a mechanism for add-in card vendors to distinguish their add-in cards from one another even though the add-in cards may have the same PCI controller on them (and, therefore, the same Vendor ID and Device ID).
30 = Expansion ROM base Address\r - Offset [33:30]\r B0 = 1 - Expansion ROM enabled\r B10:1 - Reserved\r B31:11 - base address
31 = Expansion ROM base Address\r - Offset [33:30]\r B0 = 1 - Expansion ROM enabled\r B10:1 - Reserved\r B31:11 - base address
32 = Expansion ROM base Address\r - Offset [33:30]\r B0 = 1 - Expansion ROM enabled\r B10:1 - Reserved\r B31:11 - base address
33 = Expansion ROM base Address\r - Offset [33:30]\r B0 = 1 - Expansion ROM enabled\r B10:1 - Reserved\r B31:11 - base address
34 = Capabilities pointer\r\rThis optional register is used to point to a linked list of additional capabilities implemented by this device.
35 = Reserved - Offset [3B:35]
36 = Reserved - Offset [3B:35]
37 = Reserved - Offset [3B:35]
38 = Reserved - Offset [3B:35]
39 = Reserved - Offset [3B:35]
3A = Reserved - Offset [3B:35]
3B = Reserved - Offset [3B:35]
3C = Interrupt line\r\rThe Interrupt Line register is a read/write register used to communicate interrupt line routing information between initialization code and the device driver. This register must be initialized by initialization code so a default state is not specified. The value written to the Interrupt Line register specifies the routing of the device<63><65>s INTx# pin to the system interrupt controller.
3D = Interrupr pin\r\rThe Interrupt Pin register is used to indicate which interrupt pin the bridge uses. A value of 1 corresponds to INTA#; a value of 2 corresponds to INTB#; a value of 3 corresponds to INTC#; and a value of 4 corresponds to INTD#.
3E = Min_Gnt\r\rThese read-only byte registers are used to specify the device's desired settings for Latency Timer values. For both registers, the value specifies a period of time in units of 1/4 microsecond. Values of 0 indicate that the device has no major requirements for the settings of Latency Timers. MIN_GNT is used for specifying how long a burst period the device needs assuming a clock rate of 33 MHz. MAX_LAT is used for specifying how often the device needs to gain access to the PCI bus.
3F = Max_Lat\r\rThese read-only byte registers are used to specify the device's desired settings for Latency Timer values. For both registers, the value specifies a period of time in units of 1/4 microsecond. Values of 0 indicate that the device has no major requirements for the settings of Latency Timers. MIN_GNT is used for specifying how long a burst period the device needs assuming a clock rate of 33 MHz. MAX_LAT is used for specifying how often the device needs to gain access to the PCI bus.

BIN
Tools/RwPortableX64V1.6.7/Win64/Portable/Rw.exe Normal file
View File

Binary file not shown.

8739
Tools/RwPortableX64V1.6.7/Win64/Portable/Rw.ini Normal file
View File

File diff suppressed because it is too large Load Diff

5
Tools/RwPortableX64V1.6.7/Win64/Portable/RwWeb.url Normal file
View File

@@ -0,0 +1,5 @@
[DEFAULT]
BASEURL=http://rweverything.phpnet.us
[InternetShortcut]
URL=http://rweverything.phpnet.us
Modified=D02B67F57A59C701F2

130
Tools/RwPortableX64V1.6.7/Win64/Portable/SDRSPD.IRW Normal file
View File

@@ -0,0 +1,130 @@
[INFO]
Name = SDR SDRAM SPD
00 = Number of Serial PD bytes written during module manufacturer\r 01 = 1 byte\r 02 = 2 bytes\r 03 = 3 bytes\r . .\r . .\r 80 = 128 bytes\r . .
01 = Total number of bytes in Serial PD device\r 01 = 2 bytes\r 02 = 4 bytes\r 03 = 8 bytes\r . .\r . .\r 07 = 128 bytes\r 08 = 256 bytes\r . .
02 = Fundamental memory type\r 01 = FPM\r 02 = EDO\r 03 = Pipelined Nibble\r 04 = SDR SDRAM\r 05 = ROM\r 06 = DDR SGRAM\r 07 = DDR SDRAM
03 = Number of row addresses (includes Mixed-size Row addr) This field describes the Row addressing on the module. If there is one physical bank on the module or if there are two physical banks of the same size and organization, then bits 0-3 are used to represent the number of row addresses for each physical bank. If the module has two physical banks of asymmetric size, then bits 0-3 represent the number of row addresses for physical bank 1 and bits 4-7 represent the number of row addresses for physical bank 2 (bank 2 device is 2x bank 1 device width).
04 = # Column Addresses on this assembly (includes Mixed-size Col addr)
05 = # Module Rows on this assembly
06 = Data Width of this assembly
07 = Data Width of this assembly
08 = Voltage interface standard of this assembly
09 = SDRAM Cycle time, CL=X (highest CAS latency)
0A = SDRAM Access from Clock (highest CAS latency)
0B = DIMM Configuration type (non-parity, ECC)
0C = Refresh Rate/Type
0D = Primary SDRAM Width
0E = Error Checking SDRAM width
0F = Minimum Clock Delay Back to Back Random Column Address
10 = Burst Lengths Supported
11 = # of Banks on Each SDRAM Device
12 = CAS# Latencies Supported
13 = CS# Latency
14 = Write Latency
15 = SDRAM Module Attributes
16 = SDRAM Device Attributes
17 = Min SDRAM Cycle time at CL X-1 (2nd highest CAS latency)
18 = SDRAM Access from Clock at CL X-1 (2nd highest CAS latency)
19 = Min SDRAM Cycle time at CL X-2 (3rd highest CAS latency)
1A = Max SDRAM Access from Clock at CL X-2 (3rd highest CAS latency)
1B = Min Row Precharge Time (Trp)
1C = Min Row Active to Row Active (Trrd)
1D = Min RAS to CAS Delay (Trcd)
1E = Minimum RAS Pulse Width (Tras)
1F = Density of each row on module (mixed, non-mixed sizes)
20 = Superset Information (may be used in future)
21 = Superset Information (may be used in future)
22 = Superset Information (may be used in future)
23 = Superset Information (may be used in future)
24 = Superset Information (may be used in future)
25 = Superset Information (may be used in future)
26 = Superset Information (may be used in future)
27 = Superset Information (may be used in future)
28 = Superset Information (may be used in future)
29 = Superset Information (may be used in future)
2A = Superset Information (may be used in future)
2B = Superset Information (may be used in future)
2C = Superset Information (may be used in future)
2D = Superset Information (may be used in future)
2E = Superset Information (may be used in future)
2F = Superset Information (may be used in future)
30 = Superset Information (may be used in future)
31 = Superset Information (may be used in future)
32 = Superset Information (may be used in future)
33 = Superset Information (may be used in future)
34 = Superset Information (may be used in future)
35 = Superset Information (may be used in future)
36 = Superset Information (may be used in future)
37 = Superset Information (may be used in future)
38 = Superset Information (may be used in future)
39 = Superset Information (may be used in future)
3A = Superset Information (may be used in future)
3B = Superset Information (may be used in future)
3C = Superset Information (may be used in future)
3D = Superset Information (may be used in future)
3E = SPD Data Revision Code
3F = Checksum for bytes 0-62 (00h - 3Eh)
40 = Manufacturer<65><72>s JEDEC ID code per JEP-108E
41 = Manufacturer<65><72>s JEDEC ID code per JEP-108E
42 = Manufacturer<65><72>s JEDEC ID code per JEP-108E
43 = Manufacturer<65><72>s JEDEC ID code per JEP-108E
44 = Manufacturer<65><72>s JEDEC ID code per JEP-108E
45 = Manufacturer<65><72>s JEDEC ID code per JEP-108E
46 = Manufacturer<65><72>s JEDEC ID code per JEP-108E
47 = Manufacturer<65><72>s JEDEC ID code per JEP-108E
48 = Manufacturing Location
49 = Manufacturer<65><72>s Part Number
4A = Manufacturer<65><72>s Part Number
4B = Manufacturer<65><72>s Part Number
4C = Manufacturer<65><72>s Part Number
4D = Manufacturer<65><72>s Part Number
4E = Manufacturer<65><72>s Part Number
4F = Manufacturer<65><72>s Part Number
50 = Manufacturer<65><72>s Part Number
51 = Manufacturer<65><72>s Part Number
52 = Manufacturer<65><72>s Part Number
53 = Manufacturer<65><72>s Part Number
54 = Manufacturer<65><72>s Part Number
55 = Manufacturer<65><72>s Part Number
56 = Manufacturer<65><72>s Part Number
57 = Manufacturer<65><72>s Part Number
58 = Manufacturer<65><72>s Part Number
59 = Manufacturer<65><72>s Part Number
5A = Manufacturer<65><72>s Part Number
5B = Revision Code
5C = Revision Code
5D = Manufacturing Date
5E = Manufacturing Date
5F = Assembly Serial Number
60 = Assembly Serial Number
61 = Assembly Serial Number
62 = Assembly Serial Number
63 = Manufacturer Specific Data
64 = Manufacturer Specific Data
65 = Manufacturer Specific Data
66 = Manufacturer Specific Data
67 = Manufacturer Specific Data
68 = Manufacturer Specific Data
69 = Manufacturer Specific Data
6A = Manufacturer Specific Data
6B = Manufacturer Specific Data
6C = Manufacturer Specific Data
6D = Manufacturer Specific Data
6E = Manufacturer Specific Data
6F = Manufacturer Specific Data
70 = Manufacturer Specific Data
71 = Manufacturer Specific Data
72 = Manufacturer Specific Data
73 = Manufacturer Specific Data
74 = Manufacturer Specific Data
75 = Manufacturer Specific Data
76 = Manufacturer Specific Data
77 = Manufacturer Specific Data
78 = Manufacturer Specific Data
79 = Manufacturer Specific Data
7A = Manufacturer Specific Data
7B = Manufacturer Specific Data
7C = Manufacturer Specific Data
7D = Manufacturer Specific Data
7E = Intel specification frequency
7F = Intel Specification CAS# Latency support

24
Tools/RwPortableX64V1.6.7/Win64/Portable/W697HF0.IRW Normal file
View File

@@ -0,0 +1,24 @@
[INFO]
Name = Winbond 83697HF super I/O
02 = CR02 (Default 0x00)\r B7-1: Reserved\r B0: SWRST --> Soft Reset
07 = CR07 Logical device number
20 = CR20 Device ID
21 = CR20 Device revision
22 = CR22 (Default 0xff)\r B7-5: Reserved\r B4: HMPWD\r 0: Power down\r 1: No Power down\r B3: URBPWD\r 0: Power down\r 1: No Power down\r B2: URAPWD\r 0: Power down\r 1 No Power down\r B1: PRTPWD\r 0: Power down\r 1: No Power down\r B0: FDCPWD\r 0: Power down\r 1: No Power down
23 = CR23 (Default 0x00)\r B7-1: Reserved\r B0: IPD (Immediate Power Down)\r When set to 1, it will put\r the whole chip into power\r down mode immediately
24 = CR24 (Default 0x00)\r B7: Reserved\r B6: CLKSEL (0/1 = 24/48Mhz)\r B5-4: ROM size select\r 00: 1M, 01: 2M, 10: 4M\r B3: MEMW# (0/1=Disable/Enable)\r B2: Reserved\r B1: Flash ROM Interface\r 0/1 = Enable/Disable\r B0: PNPCSV#\r 0: Default value for PnP address select registers\r 1: no default value for PnP address select registers
25 = CR25 (Default 0x00)\r B7-4: Reserved\r B3: URBTRI\r B2: URATRI\r B1: PRTTRI\r B0: FDCTRI
26 = CR26 (Default 0x00)\r B7: SEL4FDD (0/1 = 2/4 FDD)\r B6: HEFRAS - config port\r 0/1 = 2Eh/4Eh\r B5: LOCKREG\r 0: enable R/W config reg.\r 1: disable R/W config reg.\r B4: Reserved\r B3: DSFDLGRQ - FDC legacy mode IRQ & DRQ select\r B2: DSPRLGRQ - PRT legacy mode IRQ & DRQ select\r B1: DSUALGRQ - UART A legacy mode IRQ & DRQ select\r B0: DSUBLGRQ - UART B legacy mode IRQ & DRQ select
28 = CR28 (Default 0x00)\r B7-3: Reserved\r B2-0: PRTMODS2 - PRTMODS0\r 0xx Parallel Port Mode\r 100 Reserved\r 101 External FDC Mode\r 110 Reserved\r 111 External two FDC Mode
29 = CR29 GPIO1,5(50~51) & Game & MIDI port\r B7: select Game or GPIO port 1\r B6-5: Pin119\r 0/1/2/3 = MSI/WDTO#/Reserved/GP51\r B4-3: Pin120\r 0/1/2/3 = MSO/PLED/Reserved/GP50\r B2: Pin117 - 0/1 = OVT#/SMI#\r B1-0: Reserved
2A = CR2A GPIO2-5 & Flash ROM Interface Default FF if PENROM# = 0 during POR, default 00 otherwise\r B7: Pin86-89 & 91-94\r 0/1=GPIO 2/Flash IF (xD7-xD0)\r B6: Pin78-85\r 0/1=GPIO 3/Flash IF (xA7-xA0)\r B5: Pin69-74 & 76-77\r 0/1=GPIO 4/Flash IF xA15-xA10 & xA7-xA0\r B4: Pin66-68 & 95-97\r 0/1=GPIO 5/Flash IF (xA18-xA16, ROMCS#, MEMR#, MEMW#)\r B3-0: Reserved
30 = CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise)\r B7-1: Reserved\r B0 = 1 Activates the logical device
60 = CR60 (Default 0x03 if PNPCSV = 0 during POR, default 0x00 otherwise)\r select FDC I/O base address (high byte)
61 = CR61 (Default 0xF0 if PNPCSV = 0 during POR, default 0x00 otherwise)\r select FDC I/O base address (low byte)
70 = CR70 (Default 0x06 if PNPCSV = 0 during POR, default 0x00 otherwise)\r B7-4: Reserved\r B3-0: These bits select IRQ resource for FDC
74 = CR74 (Default 0x02 if PNPCSV = 0 during POR, default 0x04 otherwise)\r B7-3: Reserved\r B2-0: These bits select DRQ resource for FDC\r 0/1/2/3=DMA0/1/2/3\r 4-7: No DMA active
F0 = CRF0 (Default 0x0E) FDD Mode\r B7: FIPURDWN - internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0, DSKCHG and WP\r 0/1=pull-up turned on/off\r B6: INTVERTZ - This bit determines the polarity of all FDD interface signals\r 0/1=active low/high\r B5: DRV2EN (PS2 mode only) if logic 0, indicates a second drive is installed and is reflected in status register A\r B4: Swap Drive 0, 1 Mode\r B3-2 Interface Mode\r 3/2/1/0=AT/resv./PS2/Model30\r B1: FDC DMA Mode\r Burst/Non-Burst\r B0: Floppy Mode\r 0/1=Normal/Enhanced 3-mode
F1 = CRF1 (Default 0x00)\r B7-6: Boot Floppy\r 0/1/2/3=FDD A/B/C/D\r B5-4: Media ID1, Media ID0. reflected on FDC's Tape Drive Register B7-6\r B3-2: Density Select\r 0/1/2/3 Normal/Normal/Logic1/Logic0\r B1: DISFDDWR\r 0/1=write enable/disable\r B0: SWWP - 0: WP to determine whether the FDD is write protected or not, 1: FDD is always write-protected
F2 = CRF2 (Default 0xFF)\r B7-6: FDD D Drive Type\r B5-4: FDD C Drive Type\r B3-2: FDD B Drive Type\r B1-0: FDD A Drive Type
F4 = CRF4 (Default 0x00)\r FDD0 Selection:\r B7: Reserved\r B6: 0/1=Precomp. disable/enable\r B5: Reserved\r B4-3: DRTS1, DRTS0: Data Rate Table select (Refer to TABLE A)\r 0: Select regular & 2.88 format\r 1: 3-mode drive\r 2: 2 Meg Tape\r 3: Reserved\r B2: Reserved\r B1-0: DTYPE0, DTYPE1: Drive Type select
F5 = CRF5 (Default 0x00)\r FDD1 Selection: Same as FDD0 of CRF4

BIN
Tools/RwPortableX64V1.6.7/Win64/Portable/rw.chm Normal file
View File

Binary file not shown.