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Repository/Tools/RwPortableX64V1.6.7/Win64/Portable/PCISTD.IRW
David Wuibaille 7cc3011354 Auto-commit: 2025-10-31 08:58:35
2025-10-31 08:58:36 +01:00

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[INFO]
00 = Vendor ID - Offset [1:0]\r\rThe Vendor ID register identifies the manufacturer of the device and is assigned by PCISIG to insure uniqueness.
01 = Vendor ID - Offset [1:0]\r\rThe Vendor ID register identifies the manufacturer of the device and is assigned by PCISIG to insure uniqueness.
02 = Device ID - Offset [3:2]\r\rThe Device ID register identifies the particular device and is assigned by the vendor.
03 = Device ID - Offset [3:2]\r\rThe Device ID register identifies the particular device and is assigned by the vendor.
04 = Command - Offset [5:4]\r B0 - I/O Space Enable\r B1 - Memory Space Enable\r B2 - Bus Master Enable\r B3 - Special Cycle Enable\r B4 - Memory Write and Invalidate\r B5 - VGA Palette Snoop Enable\r B6 - Parity Error Response\r B7 - Reserved\r B8 - SERR# Enable\r B9 - Fast Back-to-Back Enable\r B10 - Interrupt Disable\r B15:11 - Reserved
05 = Command - Offset [5:4]\r B0 - I/O Space Enable\r B1 - Memory Space Enable\r B2 - Bus Master Enable\r B3 - Special Cycle Enable\r B4 - Memory Write and Invalidate\r B5 - VGA Palette Snoop Enable\r B6 - Parity Error Response\r B7 - Reserved\r B8 - SERR# Enable\r B9 - Fast Back-to-Back Enable\r B10 - Interrupt Disable\r B15:11 - Reserved
06 = Status - Offset [7:6]\r B2:0 - Reserved\r B3 - Interrupt Status\r B4 - Capabilities List\r B5 - 66 MHz Capable\r B6 - Reserved\r B7 - Fast Back-to-Back Capable\r B8 - Master Data Parity Error\r B10:9 - DEVSEL# Timing\r 00 - fast\r 01 - medium\r 02 - slow\r B11 - Signaled Target-Abort\r B12 - Received Target-Abort\r B13 - Received Master-Abort\r B14 - Signaled System Error\r B15 - Detected Parity Error
07 = Status - Offset [7:6]\r B2:0 - Reserved\r B3 - Interrupt Status\r B4 - Capabilities List\r B5 - 66 MHz Capable\r B6 - Reserved\r B7 - Fast Back-to-Back Capable\r B8 - Master Data Parity Error\r B10:9 - DEVSEL# Timing\r 00 - fast\r 01 - medium\r 02 - slow\r B11 - Signaled Target-Abort\r B12 - Received Target-Abort\r B13 - Received Master-Abort\r B14 - Signaled System Error\r B15 - Detected Parity Error
08 = Revision ID\r\rThe Revision ID register specifies a device-specific revision identifier.
09 = Class code - Programming Interface type\r\rThe Class Code register is used to identify the function of the device.
0A = Class code - Sub type\r\rThe Class Code register is used to identify the function of the device.
0B = Class code - Base type\r\rThe Class Code register is used to identify the function of the device.
0C = Cache line size\r\rThe Cacheline Size register is used when terminating a transaction that uses the Memory Write and Invalidate command and when prefetching (Memory Read Line and Memory Read Multiple commands).
0D = Latency timer\r\rThe Latency Timer register is required if a bridge is capable of a burst transfer of more than two data phases on its primary interface.
0E = Header type\r 00 - Standard PCI\r 01 - PCI-to-PCI Bridge\r 02 - Cardbus\r B7 = 1 - Multi-Function Device
0F = Built-In Self Test\r B3:0 - BIST Result\r B5:4 - Reserved\r B6 - Start BIST\r B7 - BIST Capable
10 = Base Address 0 - Offset [13:10]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
11 = Base Address 0 - Offset [13:10]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
12 = Base Address 0 - Offset [13:10]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
13 = Base Address 0 - Offset [13:10]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
14 = Base Address 1 - Offset [17:14]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
15 = Base Address 1 - Offset [17:14]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
16 = Base Address 1 - Offset [17:14]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
17 = Base Address 1 - Offset [17:14]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
18 = Base Address 2 - Offset [1B:18]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
19 = Base Address 2 - Offset [1B:18]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
1A = Base Address 2 - Offset [1B:18]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
1B = Base Address 2 - Offset [1B:18]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
1C = Base Address 3 - Offset [1F:1C]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
1D = Base Address 3 - Offset [1F:1C]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
1E = Base Address 3 - Offset [1F:1C]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
1F = Base Address 3 - Offset [1F:1C]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
20 = Base Address 4 - Offset [23:20]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
21 = Base Address 4 - Offset [23:20]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
22 = Base Address 4 - Offset [23:20]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
23 = Base Address 4 - Offset [23:20]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
24 = Base Address 5 - Offset [27:24]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
25 = Base Address 5 - Offset [27:24]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
26 = Base Address 5 - Offset [27:24]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
27 = Base Address 5 - Offset [27:24]\r\r Memory Base\r B0 = 0 - Memory space\r B2:1 - Type\r 00 - Base address is 32 bits wide\r 01 - Reserved\r 10 - Base address is 64 bits wide\r 11 - Reserved\r B3 = 1 - Memory is prefetchable\r B31:4 - Base address\r\r I/O Base\r B0 = 1 - I/O space\r B1 - Reserved\r B31:2 - Base address
28 = Cardbus CIS pointer\r - Offset [2B:28]\r\rThis optional register is used by those devices that want to share silicon between CardBus and PCI. The field is used to point to the Card Information Structure (CIS) for the CardBus card.
29 = Cardbus CIS pointer\r - Offset [2B:28]\r\rThis optional register is used by those devices that want to share silicon between CardBus and PCI. The field is used to point to the Card Information Structure (CIS) for the CardBus card.
2A = Cardbus CIS pointer\r - Offset [2B:28]\r\rThis optional register is used by those devices that want to share silicon between CardBus and PCI. The field is used to point to the Card Information Structure (CIS) for the CardBus card.
2B = Cardbus CIS pointer\r - Offset [2B:28]\r\rThis optional register is used by those devices that want to share silicon between CardBus and PCI. The field is used to point to the Card Information Structure (CIS) for the CardBus card.
2C = Subsystem vendor ID\r - Offset [2D:2C]\r\rThese registers are used to uniquely identify the add-in card or subsystem where the PCI device resides. They provide a mechanism for add-in card vendors to distinguish their add-in cards from one another even though the add-in cards may have the same PCI controller on them (and, therefore, the same Vendor ID and Device ID).
2D = Subsystem vendor ID\r - Offset [2D:2C]\r\rThese registers are used to uniquely identify the add-in card or subsystem where the PCI device resides. They provide a mechanism for add-in card vendors to distinguish their add-in cards from one another even though the add-in cards may have the same PCI controller on them (and, therefore, the same Vendor ID and Device ID).
2E = Subsystem ID - Offset [2F:2E]\r\rThese registers are used to uniquely identify the add-in card or subsystem where the PCI device resides. They provide a mechanism for add-in card vendors to distinguish their add-in cards from one another even though the add-in cards may have the same PCI controller on them (and, therefore, the same Vendor ID and Device ID).
2F = Subsystem ID - Offset [2F:2E]\r\rThese registers are used to uniquely identify the add-in card or subsystem where the PCI device resides. They provide a mechanism for add-in card vendors to distinguish their add-in cards from one another even though the add-in cards may have the same PCI controller on them (and, therefore, the same Vendor ID and Device ID).
30 = Expansion ROM base Address\r - Offset [33:30]\r B0 = 1 - Expansion ROM enabled\r B10:1 - Reserved\r B31:11 - base address
31 = Expansion ROM base Address\r - Offset [33:30]\r B0 = 1 - Expansion ROM enabled\r B10:1 - Reserved\r B31:11 - base address
32 = Expansion ROM base Address\r - Offset [33:30]\r B0 = 1 - Expansion ROM enabled\r B10:1 - Reserved\r B31:11 - base address
33 = Expansion ROM base Address\r - Offset [33:30]\r B0 = 1 - Expansion ROM enabled\r B10:1 - Reserved\r B31:11 - base address
34 = Capabilities pointer\r\rThis optional register is used to point to a linked list of additional capabilities implemented by this device.
35 = Reserved - Offset [3B:35]
36 = Reserved - Offset [3B:35]
37 = Reserved - Offset [3B:35]
38 = Reserved - Offset [3B:35]
39 = Reserved - Offset [3B:35]
3A = Reserved - Offset [3B:35]
3B = Reserved - Offset [3B:35]
3C = Interrupt line\r\rThe Interrupt Line register is a read/write register used to communicate interrupt line routing information between initialization code and the device driver. This register must be initialized by initialization code so a default state is not specified. The value written to the Interrupt Line register specifies the routing of the device<63><65>s INTx# pin to the system interrupt controller.
3D = Interrupr pin\r\rThe Interrupt Pin register is used to indicate which interrupt pin the bridge uses. A value of 1 corresponds to INTA#; a value of 2 corresponds to INTB#; a value of 3 corresponds to INTC#; and a value of 4 corresponds to INTD#.
3E = Min_Gnt\r\rThese read-only byte registers are used to specify the device's desired settings for Latency Timer values. For both registers, the value specifies a period of time in units of 1/4 microsecond. Values of 0 indicate that the device has no major requirements for the settings of Latency Timers. MIN_GNT is used for specifying how long a burst period the device needs assuming a clock rate of 33 MHz. MAX_LAT is used for specifying how often the device needs to gain access to the PCI bus.
3F = Max_Lat\r\rThese read-only byte registers are used to specify the device's desired settings for Latency Timer values. For both registers, the value specifies a period of time in units of 1/4 microsecond. Values of 0 indicate that the device has no major requirements for the settings of Latency Timers. MIN_GNT is used for specifying how long a burst period the device needs assuming a clock rate of 33 MHz. MAX_LAT is used for specifying how often the device needs to gain access to the PCI bus.
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